Shift Register and Gate Driving Circuit Using the Same

Abstract

Disclosed are a shift register that shows excellent operation reliability with elements less than those of the conventional structure and a gate driving circuit using the shift register. The gate driving circuit comprises each of a plurality of shift registers sequentially connected and respectively supplying scan signals to a plurality of gate lines of a display device.

1 - 15 . (canceled) 
     
     
         16 . A gate driving circuit comprising a plurality of shift registers sequentially connected and respectively supplying scan signals to a plurality of gate lines of a display device, each shift register comprising:
 an input unit which receives an output signal from a previous shift register of the shift register, and outputs the output signal to a first node;   an inverter unit which connects with the first node, generates an inverting signal for a signal of the first node, and outputs the inverting signal to a second node;   an output unit which comprises a pull-up unit connecting to the first node, for activating a first clock signal by the signal of the first node and outputting the first clock signal as an output signal to the corresponding gate line, and a pull-down unit for activating and outputting a pull-down output signal to the corresponding gate line by a signal of the second node; and   a reset unit which periodically resets the first node by a second clock signal,   wherein the inverter unit is controlled by the second clock signal.   
     
     
         17 . The gate driving circuit according to  claim 16 , wherein an input signal to an input unit of the first or last shift register among the plurality of shift registers is a pulse type input start signal. 
     
     
         18 . The gate driving circuit according to  claim 16 , wherein the inverter unit comprises:
 a first switching device which comprises a gate terminal to receive the second clock signal, a drain terminal to receive a bias voltage, and a source terminal connected to the second node; and   a second switching device which comprises a gate terminal connected to the first node, a drain terminal connected to the second node, and a source terminal connected to a low level voltage terminal.   
     
     
         19 . The gate driving circuit according to  claim 18 , wherein the second clock signal is applied once per 4H period. 
     
     
         20 . The gate driving circuit according to  claim 16 , wherein the reset unit comprises a switching device which comprises a gate to receive the second clock signal, a drain connected to the first node, and a source connected to a low level voltage terminal. 
     
     
         21 . The gate driving circuit according to  claim 20 , wherein the second clock signal is applied once per 4H period. 
     
     
         22 . The gate driving circuit according to  claim 16 , wherein the first clock signal is a clock signal CLK 1  and or CLK 3  and the second clock signal is a clock signal CLK 2  and or CLK 4 , and the four clock signals CLK 1 , CLK 2 , CLK 3  and CLK 4  are different in a phase of 1H in cyclic sequence. 
     
     
         23 . A shift register comprising
 a first switching device which comprises a gate terminal and drain terminal connected in common to an output terminal of a previous shift register, and a source connected to a first node;   a second switching device which comprises a gate terminal connected to the first node, a drain terminal to receive a first clock signal, and a source terminal connected to an output terminal of the shift register;   a third switching device which comprises a gate terminal connected to a second node, a drain terminal connected to the output terminal of the shift register, and a source terminal connected to a low level voltage terminal;   a fourth switching device which comprises a gate terminal connected to the gate terminal of the third switching device and the second node, a drain terminal connected to the first node, and a source terminal connected to the low level voltage terminal;   a fifth switching device which comprises a gate terminal to receive a second clock signal, a drain terminal to receive a bias voltage, and a source terminal connected to the second node;   a sixth switching device which comprises a gate terminal connected to the first node, a drain terminal connected to the second node and the source terminal of the fifth switching device, and a source terminal connected to the low level voltage terminal; and   a seventh switching device which comprises a gate terminal to receive the second clock signal, a drain terminal connected to the first node, and a source terminal connected to the low level voltage terminal.