Method and Apparatus for 3D Capture Synchronization

Abstract

In accordance with an example embodiment of the present invention, disclosed is a method and an apparatus thereof for receiving a first command via a first interface that is addressable by a first address and receiving a second command via a second interface that is addressable by a second address.

1 - 18 . (canceled) 
     
     
         19 . An apparatus comprising:
 a first interface addressable by a first address; and   a second interface addressable by a second address.   
     
     
         20 . An apparatus of  claim 19 , further comprising a clock input separate from the first interface and the second interface, the clock input configured to receive a clock signal, wherein the apparatus is configured to receive the first address responsive to the clock signal. 
     
     
         21 . An apparatus of  claim 19 , wherein the first address is a unique address and the second address is shared address. 
     
     
         22 . An apparatus of  claim 21 , wherein the shared address is the same for each of at least two peripheral devices of the same type connected to the same bus. 
     
     
         23 . An apparatus of  claim 19 , wherein the first interface is configured to receive individual commands, and the second interface is configured to receive group commands. 
     
     
         24 . An apparatus of  claim 19 , wherein the apparatus is inter-integrated circuit-bus compatible. 
     
     
         25 . An apparatus of  claim 19 , wherein the apparatus is a camera module. 
     
     
         26 . An apparatus of  claim 25 , wherein the first interface and the second interface are camera control interfaces. 
     
     
         27 . A system comprising:
 a host device; and   an apparatus comprising:
 a first interface addressable by a first address; and
 a second interface addressable by a second address. 
 
   
     
     
         28 . A system of  claim 27 , wherein said at least two peripheral devices are connected to the host device via an inter-integrated circuit-bus. 
     
     
         29 . A system of  claim 27 , wherein group commands are received at the same time in each of the at least two peripheral devices of the same type connected to the host device. 
     
     
         30 . A system of  claim 27 , wherein only one of the at least two peripheral devices is enabled to send an acknowledge signal to the host device as a response to a group command. 
     
     
         31 . A method comprising:
 receiving a first command via a first interface addressable by a first address; and   receiving a second command via a second interface addressable by a second address.   
     
     
         32 . A method of  claim 31 , further comprising:
 receiving a clock signal at a clock input, and   subsequently receiving via the first interface a unique address to replace said first address.   
     
     
         33 . A method of  claim 31 , wherein the second address is a shared address, the shared address being the same for each of at least two peripheral devices of the same type connected to the same bus. 
     
     
         34 . A method of  claim 31 , further comprising storing an indication indicating whether a peripheral device is an acknowledging peripheral device, and
 in case the peripheral device is an acknowledging peripheral device, sending an acknowledge signal in response to a group command received via the second interface.   
     
     
         35 . A method of  claim 34 , wherein the group command is received at the same time in each of at least two peripheral devices of the same type connected to the same bus. 
     
     
         36 . A non-transitory computer-readable medium that contains software program instructions, where execution of the software program instructions by at least one data processor cause an apparatus at least to perform:
 receive a first command via a first interface addressable by a first address; and   receive a second command via a second interface addressable by a second address.   
     
     
         37 . A non-transitory computer-readable medium of  claim 36 , wherein the apparatus is further caused to perform:
 receive a clock signal at a clock input; and   receive via the first interface a unique address to replace said first address.   
     
     
         38 . A non-transitory computer-readable medium of  claim 36 , wherein the second address is a shared address, the shared address being the same for each of at least two peripheral devices of the same type connected to the same bus.