Semiconductor device and manufacturing method thereof

Abstract

Such a device is disclosed that includes: redundancy circuits for replacing defective memory cells included in a memory cell array; an electrical fuse circuit that stores addresses of the defective memory cells; a data determination circuit that generates a determination signal by determining whether test data read from the memory cell array is correct or incorrect; and an analysis circuit that supplies, in a first operation mode, the electrical fuse circuit with an address signal supplied when the determination signal is activated, and supplies, in a second operation mode, the electrical fuse circuit with an address signal supplied when a data mask signal supplied from outside is activated irrespective of the determination signal.

What is claimed is: 
     
         1 . A method for manufacturing a memory device comprising the steps of:
 performing a first operation test on a memory array formed on a semiconductor wafer;   analyzing addresses of first defective memory cells detected by the first operation test to identify first defective addresses;   performing primary replacement to replace the first defective memory cells with first redundant memory cells based on the first defective addresses;   dicing the semiconductor wafer after performing the primary replacement to obtain a memory chip on which the memory array is integrated;   packaging a plurality of semiconductor chips including at least the memory chip to obtain a packaged memory device;   performing a second operation test on the packaged memory device;   analyzing addresses of second defective memory cells detected by the second operation test to identify second defective addresses; and   performing secondary replacement to replace the second defective memory cells with second redundant memory cells based on the second defective addresses.   
     
     
         2 . The method of  claim 1  wherein performing primary replacement comprises programming optical fuses with first defective addresses. 
     
     
         3 . The method of  claim 2  wherein performing secondary replacement comprises programming electrical fuses with second defective addresses. 
     
     
         4 . The method of  claim 1  wherein performing secondary replacement comprises programming electrical fuses with second defective addresses. 
     
     
         5 . The method of  claim 1  wherein first defective addresses comprise row addresses and column addresses. 
     
     
         6 . The method of  claim 1  wherein second defective addresses comprise row addresses and column addresses. 
     
     
         7 . The method of  claim 1  wherein packaging comprises stacking the plurality of semiconductor chips. 
     
     
         8 . The method of  claim 7  wherein the plurality of semiconductor chips are connected with through silicon vias. 
     
     
         9 . The method of  claim 1  wherein the plurality of semiconductor chips comprises a control circuit. 
     
     
         10 . The method of  claim 9  wherein the control circuit performs the second operation test. 
     
     
         11 . The method of  claim 9  wherein the control circuit comprises fuses for performing secondary replacement. 
     
     
         12 . The method of  claim 11  wherein the fuses for performing secondary replacement are electrical fuses. 
     
     
         13 . The method of  claim 1  wherein the memory device is a DRAM.