System having one or more memory devices

Abstract

A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

What is claimed is: 
     
         1 . A system comprising:
 a memory controller having a first number of output ports, the memory controller providing a command to access maximum data width configuration data from one output port of the first number of output ports; and,   a memory device having an input/output register for storing the maximum data width configuration data, a second number of data input pads and the second number of data output pads, the memory device receiving the command at one data input pad of the second number of data input pads and providing the maximum data width configuration data from one data output pad of the second number of data output pads.