Method for manufacturing a chip from a system definition

Abstract

A method for manufacturing a chip from a system definition, the system definition describing a plurality of cells, buses and external I/O. The cell definitions are defined by providing two libraries, a first containing a superset of cell definitions; and a second a plurality of HDL definitions of cells selected from the first library. The method further included creating the system definition from the second library, a bus definition, and an external I/O definition.

1 . A method for manufacturing a chip, comprising:
 a. defining a first library of cell definitions, wherein a cell definition comprises a superset;   b. selecting from the first library the respective superset for each cell;   c. generating from the selected superset, a hardware description code;   d. verifying the correctness of the hardware description code;   e. storing the generated and correct hardware description code for each selected superset into the second library;   f. specifying a system by creating a system definition, the system definition comprising:
 i. a selection, comprising a plurality of hardware description codes, from the second library for each cell in the system; 
 ii. a hardware description code of a bus system; and 
 iii. a hardware description code of external ports; 
   g. combining and connecting the plurality of cells, bus system and external ports;   h. emitting system level code for synthesis;   i. verifying the correctness of the system level code; and   j. fabricating a chip from the emitted, verified system level code.   
     
     
         2 . The method manufacturing a chip further including selecting a specific bus width for specific connections. 
     
     
         3 . The method for manufacturing a chip further including defining specific clock frequencies for specific parts of the chip. 
     
     
         4 . The method for manufacturing a chip according to the  claim 1  further including decoupling some cells from other cells for allowing different clock frequencies. 
     
     
         5 . The method for manufacturing a chip according to  claim 1  further including the step of at least one of removing and inserting registers in at least one datapath to optimize at least one of performance, area, power dissipation and latency. 
     
     
         6 . The method for manufacturing a chip according to  claim 1  wherein at least some of the cells comprise one or more processors.