Method of fabricating semiconductor device

Abstract

A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate;   a gate dielectric layer disposed on the substrate and comprising an oxide;   a gate electrode disposed on the gate dielectric layer, wherein the gate electrode has opposite sidewall surfaces;   a mask disposed on the gate electrode, wherein the mask has opposite sidewall surfaces aligned with the sidewall surfaces of the gate electrode, respectively;   a first capping pattern extending over the sidewall surfaces of the gate electrode and the mask and comprising an oxide; and   a second capping pattern disposed on the first capping pattern and comprising a nitride.   
     
     
         2 . The semiconductor device as set forth in  claim 1 , further comprising:
 a spacer disposed on the second capping pattern and comprising a nitride.   
     
     
         3 . The semiconductor device as set forth in  claim 1 , wherein the second capping pattern has a greater thickness than the first capping pattern. 
     
     
         4 . The semiconductor device as set forth in  claim 1 , wherein the substrate has a first impurity region whose boundary is located adjacent opposite sides of the gate electrode, a second impurity region whose boundary is located adjacent an outer side of the second capping pattern, and a halo region at a side of the second impurity region,
 the first and second impurity regions including impurities of the same conductivity type but of different concentrations, and the halo region including impurities of a different conductivity type from that of the first and second impurity regions.   
     
     
         5 . The semiconductor device as set forth in  claim 1 , wherein the gate electrode includes a first conductive pattern of silicon and a second conductive pattern of a metal or a metal compound.