US2014337897A1PendingUtilityA1

Systems And Methods For Receiving And Transferring Video Information

Assignee: BROADCOM CORPPriority: Jun 5, 2008Filed: May 16, 2014Published: Nov 13, 2014
Est. expiryJun 5, 2028(~1.9 yrs left)· nominal 20-yr term from priority
H04N 21/4147H04N 21/426H04N 21/6193H04L 27/36H03M 13/15H03M 13/1102H04N 21/4183H04N 21/4305H03M 13/1515H04L 27/38H03M 13/2957
55
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Claims

Abstract

Devices and methods for receiving and/or processing digital data. The devices may include a satellite modem, a transport module, and/or a processing module. The satellite modem, the transport module and/or the processing module may be formed on a single semiconductor substrate.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor chip comprising:
 a satellite modem operable to receive at least one satellite signal and generate at least one data stream from the satellite signal, the satellite modem being formed on a semiconductor substrate;   a data transport processor operable to receive the data stream and generate at least one decodable stream, the data transport processor being formed on the semiconductor substrate; and   a decoder operable to receive the at least one decodable stream and generate at least one decoded stream, the decoder being formed on the semiconductor substrate.   
     
     
         2 . The semiconductor chip of  claim 1  wherein the data transport processor is operable to store the decodable stream in a memory on the semiconductor substrate and the decoder is operable to retrieve the decodable stream from the memory. 
     
     
         3 . The semiconductor chip of  claim 1  wherein the data transport processor is operable to receive a first input and a second input from the satellite modem and the first input is synchronized with the second input. 
     
     
         4 . The semiconductor chip of  claim 3  wherein the first input and the second input are synchronized to a program clock reference timebase. 
     
     
         5 . The semiconductor chip of  claim 3  wherein the first input is a parallel input. 
     
     
         6 . The semiconductor chip of  claim 1  further comprising a personal video recorder interface that is formed on the semiconductor substrate. 
     
     
         7 . The semiconductor chip of  claim 6  further comprising a buffer for buffering data flow between the transport processor and the personal video recorder interface, the buffer being formed on the semiconductor substrate. 
     
     
         8 . The semiconductor chip of  claim 7  further comprising a security module formed on the substrate and in communication with the buffer, the security module being configured to perform a security operation on data for storage in the buffer. 
     
     
         9 . A semiconductor chip comprising:
 a satellite modem for receiving at least one satellite signal, the satellite modem comprising a tuner and a system oscillator on a semiconductor substrate, the system oscillator being operable to generate a primary timing signal for the tuner receiving the at least one satellite signal;   a data transport processor operable to receive the at least one satellite signal and generate at least one stream; and   a data processing module operable to receive and process the at least one stream.   
     
     
         10 . The semiconductor chip of  claim 9  wherein the satellite modem comprises a demodulator, the demodulator being synchronized based on the primary timing signal. 
     
     
         11 . The semiconductor chip of  claim 9  further comprising a display interface module, the display interface module being synchronized based on the primary timing signal. 
     
     
         12 . The semiconductor chip of  claim 9  wherein the data transport processor is synchronized based on the primary timing signal from the satellite modem. 
     
     
         13 . The semiconductor chip of  claim 9  wherein the data processing module is synchronized based on the primary timing signal from the satellite modem. 
     
     
         14 . The semiconductor chip of  claim 9  wherein the data processing module comprises a decoder operable to receive the at least one stream and generate at least one decoded stream and the decoder is synchronized based on the primary timing signal from the satellite modem. 
     
     
         15 . The semiconductor chip of  claim 9  further comprising a personal video recorder formed on the semiconductor substrate, the personal video recorder being synchronized based on the primary timing signal form the satellite modem. 
     
     
         16 . The semiconductor chip of  claim 15  further comprising a buffer for buffering data flow between the transport processor and the personal video recorder, the buffer being formed on the semiconductor substrate. 
     
     
         17 . A semiconductor chip comprising:
 a satellite antenna controller configured to control a plurality of antennas, the satellite controller being formed on a semiconductor substrate;   a satellite tuner for receiving at least one satellite signal, the satellite tuner being formed on the semiconductor substrate;   a data transport processor operable to receive the at least one satellite signal and generate at least one decodable stream, the data processor being formed on the semiconductor substrate; and   a decoder operable to receive the at least one decodable stream and generate at least one decoded stream, the decoder being formed on the semiconductor substrate.   
     
     
         18 . The semiconductor chip of  claim 17  wherein satellite antenna controller is configured to generate an antenna control signal in response to the satellite signal received from the satellite tuner. 
     
     
         19 . The semiconductor chip of  claim 17  wherein the data transport processor is operable to store the decodable stream in a memory on the semiconductor substrate and the decoder is operable to retrieve the decodable stream from the memory. 
     
     
         20 . The semiconductor chip of  claim 17  wherein the data transport processor is operable to receive a first input and a second input from the satellite tuner and the first input is synchronized with the second input.

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