Program Binding System, Method and Software for a Resilient Integrated Circuit Architecture

Abstract

The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary program binding method includes assigning a first action to a first computational element having a first type; assigning a second action to a second computational element having a second type; and establishing a first data routing, through a selected communication element, between the first computational element and the second computational element. In the event of detection of a fault with a composite circuit element or a communication element, the various actions may be re-assigned and new data routings established.

It is claimed: 
     
         1 . A program binding method for an integrated circuit, the method implemented using one or more processors, the integrated circuit having a plurality of cluster zones, each cluster zone of the plurality of cluster zones having a plurality of computational elements having a plurality of types and having an interconnect coupling each output of a computational element to each input of a computational element of the plurality of computational elements in the cluster zone, the integrated circuit having a plurality of intercluster queues coupling one or more interconnects of the plurality of cluster zones, the method comprising:
 using one or more processors, assigning a first action to a first computational element having a first type of the plurality of types of computational elements, the first computational element in a first cluster zone of the plurality of cluster zones;   using one or more processors, assigning a second action to a second computational element having a second type of the plurality of types of computational elements, the second computational element in the first cluster zone or in a second cluster zone of the plurality of cluster zones;   using one or more processors, establishing a first data routing between the first computational element and the second computational element through a first interconnect of the first cluster zone or through a first intercluster queue, the first intercluster queue coupling the first interconnect to a second interconnect of the second cluster zone.   
     
     
         2 . The processor-implemented method of  claim 1 , wherein each computational element of the plurality of computational elements has one or more contexts, and wherein the assignments of the first action and the second action are to one or more contexts of the first and second computational elements. 
     
     
         3 . The processor-implemented method of  claim 1 , further comprising:
 using one or more processors, determining available circuit resources on the integrated circuit.   
     
     
         4 . The processor-implemented method of  claim 1 , further comprising:
 using one or more processors, determining whether the first action has a proximity constraint, and when the first action has a proximity constraint, determining whether the first cluster zone has both the first and second types of computational elements.   
     
     
         5 . The processor-implemented method of  claim 1 , wherein the first action corresponds to a function of the first type of computational element and wherein the second action corresponds to a function of the second type of computational element. 
     
     
         6 . The processor-implemented method of  claim 1 , wherein the one or more processors comprise at least one processor of the integrated circuit and wherein the method is performed by the at least one processor of the integrated circuit following execution of a boot program. 
     
     
         7 . The processor-implemented method of  claim 1 , wherein the method is performed by a computing system comprising the one or more processors, and wherein the method further comprises:
 loading the assignments and routing information into a memory of the integrated circuit.   
     
     
         8 . The processor-implemented method of  claim 1 , further comprising:
 using one or more processors, upon detection of a fault in the first intercluster queue, establishing a second data routing between the first computational element and the second computational element through a second intercluster queue, the second intercluster queue coupling the first interconnect to the second interconnect; or   using one or more processors, upon detection of a fault in the first computational element, assigning the first action to a third computational element having the first type, and establishing a second data routing between the third computational element and the second computational element through an interconnect of the plurality of interconnects or through an intercluster queue of the plurality of intercluster queues.   
     
     
         9 . An integrated circuit comprising:
 a plurality of cluster zones, each cluster zone of the plurality of cluster zones having a plurality of computational elements having a plurality of types;   a plurality of interconnects, each cluster zone of the plurality of cluster zones having an interconnect coupling each output of a computational element to each input of a computational element of the plurality of computational elements of the cluster zone;   a plurality of intercluster queues coupling one or more interconnects of the plurality of cluster zones; and   one or more processors coupled to the plurality of computational elements, the one or more processors to assign a first action to a first computational element having a first type of the plurality of types of computational elements, the first computational element in a first cluster zone of the plurality of cluster zones; to assign a second action to a second computational element having a second type of the plurality of types of computational elements, the second computational element in the first cluster zone or in a second cluster zone of the plurality of cluster zones; and to establish a first data routing between the first computational element and the second computational element through a first interconnect of the first cluster zone or through a first intercluster queue, the first intercluster queue coupling the first interconnect to a second interconnect of the second cluster zone.   
     
     
         10 . The integrated circuit of  claim 9 , wherein each computational element of the plurality of computational elements has one or more contexts, and wherein the one or more processors further are to assign the first action and the second action to one or more contexts of the first and second computational elements. 
     
     
         11 . The integrated circuit of  claim 9 , wherein the one or more processors further are to determine availability of the plurality of computational elements by performing a self-test of the integrated circuit. 
     
     
         12 . The integrated circuit of  claim 9 , wherein the one or more processors further are to determine whether the first action has a proximity constraint, and when the first action has a proximity constraint, further are to determine whether the first cluster zone has both the first and second types of computational elements. 
     
     
         13 . The integrated circuit of  claim 9 , wherein the first action corresponds to a function of the first type of computational element and wherein the second action corresponds to a function of the second type of computational element. 
     
     
         14 . The integrated circuit of  claim 9 , wherein the one or more processors further are to execute a boot program prior to assigning the first and second actions and establishing the first data routing. 
     
     
         15 . The integrated circuit of  claim 9 , wherein the one or more processors, upon detection of a fault in the first intercluster queue, further are to establish a second data routing between the first computational element and the second computational element through a second intercluster queue, the second intercluster queue coupling the first interconnect to the second interconnect; or upon detection of a fault in the first computational element, further are to assign the first action to a third computational element having the first type; and to establish a third data routing between the third computational element and the second computational element through an interconnect of the plurality of cluster zones or through an intercluster queue of the plurality of intercluster queues. 
     
     
         16 . A system for programming an integrated circuit, the integrated circuit having a plurality of cluster zones, each cluster zone of the plurality of cluster zones having a plurality of computational elements having a plurality of types and having an interconnect coupling each output of a computational element to each input of a computational element of the plurality of computational elements in the cluster zone, the integrated circuit having a plurality of intercluster queues coupling the interconnects of predetermined cluster zones of the plurality of cluster zones, the system comprising:
 a memory; and   one or more processors coupled to the memory, the one or more processors to assign a first action to a first computational element having a first type of the plurality of types of computational elements, the first computational element in a first cluster zone of the plurality of cluster zones; to assign a second action to a second computational element having a second type of the plurality of types of computational elements, the second computational element in the first cluster zone or in a second cluster zone of the plurality of cluster zones; and to establish a first data routing between the first computational element and the second computational element through a first interconnect of the first cluster zone or through a first intercluster queue, the first intercluster queue coupling the first interconnect to a second interconnect of the second cluster zone.   
     
     
         17 . The system of  claim 16 , wherein each computational element of the plurality of computational elements has one or more contexts, and wherein the one or more processors further are to assign the first action and the second action to one or more contexts of the first and second computational elements. 
     
     
         18 . The system of  claim 16 , wherein the one or more processors, when the first action has a proximity constraint, further are to determine whether the first cluster zone has both the first and second types of computational elements. 
     
     
         19 . The system of  claim 16 , wherein the one or more processors, upon detection of a fault in the first intercluster queue, further are to establish a second data routing between the first computational element and the second computational element through a second intercluster queue, the second intercluster queue coupling the first interconnect to the second interconnect. 
     
     
         20 . The system of  claim 16 , wherein the one or more processors, upon detection of a fault in the first computational element, further are to assign the first action to a third computational element having the first type; and to establish a second data routing between the third computational element and the second computational element through an interconnect of the plurality of interconnects of the plurality of cluster zones or through an intercluster queue of the plurality of intercluster queues.