Circuit and method of adjusting system clock in low voltage detection, and low voltage reset circuit

Abstract

The present invention discloses a circuit and a method of adjusting system clock in low voltage detection, and a low voltage reset circuit. The circuit of adjusting system clock in low voltage detection comprises: a clock generator for supplying a clock to at least one circuit in a system; and a low voltage reset circuit for generating an adjustment signal according to a detected voltage level, so that the clock generator adjusts or stops the clock supplied to the at least one circuit in the system.

What is claimed is: 
     
         1 . A low voltage reset circuit comprising:
 a voltage division circuit dividing a supplied voltage to generate multiple reference voltages;   a comparator circuit comparing a voltage signal related to the supplied voltage with the multiple reference voltages; and   a logic circuit determining whether to generate an adjustment signal according to the comparison result.   
     
     
         2 . The low voltage reset circuit of  claim 1 , wherein the logic circuit further decides whether to generate a reset signal according to the comparison result. 
     
     
         3 . The low voltage reset circuit of  claim 1 , wherein the adjustment signal is generated when a level of the supplied voltage is lower than a predetermined first threshold value. 
     
     
         4 . The low voltage reset circuit of  claim 1 , wherein the adjustment signal is not generated when a level of the supplied voltage is lower than a predetermined second threshold value. 
     
     
         5 . The low voltage reset circuit of  claim 2 , wherein the reset signal is generated when the level of the supplied voltage is lower than a predetermined second threshold value. 
     
     
         6 . The low voltage reset circuit of  claim 2 , wherein the reset signal is not generated when the level of the supplied voltage is lower than a predetermined third threshold value.