Coarse-Grained Data Processor Having Both Global and Direct Interconnects

Abstract

A data processor having a plurality of coarse-grained data processing elements arranged in rows and columns, an interconnect structure comprising both global and direct interconnects, the global interconnects interconnecting the coarse-grained data processing elements globally and the direct interconnects interconnecting adjacent data processing elements.

1 . Apparatus comprising:
 a plurality of coarse-grained data processing elements arranged in rows and columns;   an interconnect structure, comprising:
 a plurality of global, multi-bit interconnects globally interconnecting the plurality of coarse-grained data processing elements; and 
 a plurality of direct, multi-bit direct interconnects, wherein an output of a first data processing element is interconnected to an input of an adjacent data processing element. 
   
     
     
         2 . Apparatus according to  claim 1 , wherein each of the plurality of coarse-grained data processing elements comprises:
 an arithmetic unit having at least one multiplier and at least one adder;   a plurality of data inputs and a plurality of data outputs connected to the global, multi-bit interconnect; and   a plurality of data registers, wherein
 a) a first subset of the plurality of data registers are connected to the data inputs, 
 b) a second subset of the plurality of data registers are connected to store internal data, 
 c) a third subset of the plurality of data registers are connected for data output. 
   
     
     
         3 . Apparatus according to  claim 1 , wherein at least one input register of a first coarse-grained data processing element of said plurality of coarse-grained data processing elements is directly connected to an input of an adjacent coarse-grained data processing element of said coarse-grained data processing elements via an output of the first coarse-grained data processing element. 
     
     
         4 . Apparatus according to  claim 2 , wherein at least one of the direct, multi-bit, interconnects of said plurality of direct, multi-bit interconnects bypasses the arithmetic unit of at least one of the plurality of coarse-grained, data processing elements. 
     
     
         5 . Apparatus according to  claim 1 , wherein at least one input register of a first coarse-grained data processing element of said plurality of coarse-grained data processing elements is directly connected to an input of an adjacent coarse-grained data processing element of said coarse-grained data processing elements via an output register of the first coarse-grained data processing elements. 
     
     
         6 . Apparatus according to  claim 1 , wherein the direct, multi-bit interconnects are configured for transmitting FIR filter data. 
     
     
         7 . A configurable data processing device comprising:
 an array of configurable cells; and   a global configurable network interconnecting the configurable cells for transferring data globally including the transfer of data between configurable cells;   wherein:   each of at least some of the configurable cells is configurable in function and comprises a data processing unit that includes a multiplier, at least two input registers and at least one output register; and   for each of a number of pairs of adjacent ones of the at least some of the configurable cells, in addition to the global configurable network interconnection, a next neighbor connection is provided between the adjacent cells of the pair, allowing for a direct next neighbor data transfer between the adjacent cells of the pair and bypassing the global configurable network.   
     
     
         8 . The configurable data processing device according to  claim 1 , wherein the next neighbor connection is a direct connection from a cell output to a cell input of an adjacent cell without a connection to the global configurable network. 
     
     
         9 . The configurable data processing device according to  claim 2 , wherein the adjacent cells connected via the next neighbor connection are two configurable cells a first configurable cell physically disposed in direct contact with a second configurable cell. 
     
     
         10 . Apparatus comprising:
 an array of data processing cores;   a bus structure interconnecting the array of data processing cores; wherein   each of the cores is adapted for receiving and executing opcodes and processing as part of a sequence a plurality data words.   
     
     
         11 . Apparatus according to  claim 10 , wherein each of the array of data processing cores is adapted for SIMD operations. 
     
     
         12 . Apparatus according to  claim 10 , wherein each of the array of data processing cores comprises an ALU to execute at least one of ADD, SUB, and MUL instructions. 
     
     
         13 . Apparatus according to  claim 10 , wherein each of the array of data processing cores comprises an ALU to execute count-leading-zeros (CLZ) instruction. 
     
     
         14 . Apparatus according to  claim 10 , where each of the array of data processing cores comprises an internal register file. 
     
     
         15 . Apparatus according to  claim 10 , further comprising at least one internal data register file. 
     
     
         16 . Apparatus according to  claim 10 , wherein each of the array of data processing cores comprises a program counter. 
     
     
         17 . Apparatus according to  claim 10 , further including at least one program counter. 
     
     
         18 . Apparatus according to  claim 10 , wherein each of the data processing cores comprises multiple execution stages. 
     
     
         19 . Apparatus according to  claim 18 , wherein the multiple execution stages comprises fetch, the code and execute. 
     
     
         20 . Apparatus according to  claim 10 , further comprising multiple execution stages. 
     
     
         21 . Apparatus according to  claim 20 , wherein the multiple execution stages comprises fetch, the code and execute. 
     
     
         22 . Apparatus according to  claim 10 , wherein each of the array of data processing cores conditionally executes instructions by testing an ALU flag, and depending upon the state of the ALU flag, either executing or omitting the execution of an instruction. 
     
     
         23 . Apparatus according to  claim 10 , further comprising were in one or more of the array of data processing cores are responsive to a wait command. 
     
     
         24 . Apparatus according to  claim 23 , wherein the way command is adapted to stop execution into a specific event fulfills a specific condition. 
     
     
         25 . Apparatus according to  claim 10 , further including a microprocessor, a cache and a register interface, wherein said the array of data processing cores and said bus structure are connected to said microprocessor via said cache and register interface. 
     
     
         26 . Apparatus according to  claim 10 , further including a clock having a configurable frequency. 
     
     
         27 . Apparatus according to  claim 26 , further comprising a voltage control responsive to said configurable frequency. 
     
     
         28 . Apparatus according to  claim 10 , wherein at least some of the data processing cores is adapted to repeatedly process the received instructions.