Pads including curved sides and related electronic devices, structures, and methods

Abstract

An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.

1 .- 22 . (canceled) 
     
     
         23 . An electronic device comprising:
 a substrate; and   a plurality of spaced apart pads on the substrate, wherein each of the pads includes first, second, third, and fourth sides, wherein the first and third sides are opposite sides that are substantially straight, and wherein the second and fourth sides are opposite sides that are curved.   
     
     
         24 . The electronic device of  claim 23  wherein the plurality of pads are arranged in linear columns in a direction that is parallel with the first and third sides, and wherein a center line connecting centers of adjacent pads of different columns defines an angle of at least 60 degrees and less than 90 degrees relative to the direction that is parallel with the first and third sides. 
     
     
         25 . The electronic device of  claim 23  wherein one of the second and fourth sides is concave and the other of the second and fourth sides is convex. 
     
     
         26 . The electronic device of  claim 25  wherein the plurality of pads are arranged in linear columns, wherein pads of a first column are arranged with the convex sides pointing in a first direction parallel to a direction of the columns, wherein pads of a second column are arranged with the convex sides pointing in a second direction parallel to the direction of the columns, and wherein the first and second directions are opposite directions. 
     
     
         27 . The electronic device of  claim 23  wherein the substrate includes a plurality of memory cell transistors, and wherein each of the spaced apart pads is electrically coupled to a source/drain region of a respective one of the memory cell transistors. 
     
     
         28 . The electronic device of  claim 27  further comprising:
 a plurality of memory cell capacitors wherein each of the memory cell capacitors is electrically coupled to a respective one of the pads. 
 
     
     
         29 . An electronic device comprising:
 a substrate; and   a plurality of spaced apart pads on the substrate, wherein each of the pads includes first and second opposing sides wherein the first side is concave and the second side is convex.   
     
     
         30 . The electronic device of  claim 29  wherein each of the pads includes third and fourth opposing sides extending between the first and second sides, and wherein the third and fourth sides are opposite sides that are substantially straight. 
     
     
         31 . The electronic device of  claim 29  wherein the plurality of pads are arranged in linear columns in a direction that is parallel with the first and third sides, and wherein a center line connecting centers of adjacent pads of different columns defines an angle of at least 60 degrees and less than 90 degrees relative to the direction that is parallel with the first and third sides. 
     
     
         32 . The electronic device of  claim 29  wherein the plurality of pads are arranged in linear columns, wherein pads of a first column are arranged with the convex sides pointing in a first direction parallel to a direction of the columns, wherein pads of a second column are arranged with the convex sides pointing in a second direction parallel to the direction of the columns, and wherein the first and second directions are opposite directions. 
     
     
         33 . The electronic device of  claim 29  wherein the substrate includes a plurality of memory cell transistors, and wherein each of the spaced apart pads is electrically coupled to a source/drain region of a respective one of the memory cell transistors. 
     
     
         34 . The electronic device of  claim 33  further comprising:
 a plurality of memory cell capacitors wherein each of the memory cell capacitors is electrically coupled to a respective one of the pads. 
 
     
     
         35 . An electronic device comprising:
 a substrate; and   a plurality of spaced apart pads on the substrate, wherein the plurality of pads are arranged in linear columns, and wherein a center line connecting centers of adjacent pads of different columns defines an angle of at least 60 degrees and less than 90 degrees relative to a direction of the columns.   
     
     
         36 . The electronic device of  claim 35  wherein each of the pads includes first, second, third, and fourth sides, wherein the first and third sides are opposite sides that are substantially straight, and wherein the second and fourth sides are opposite sides that are curved. 
     
     
         37 . The electronic device of  claim 36  wherein one of the second and fourth sides is concave and the other of the second and fourth sides is convex. 
     
     
         38 . The electronic device of  claim 37  wherein pads of a first column are arranged with the convex sides pointing in a first direction parallel to the direction of the columns, wherein pads of a second column are arranged with the convex sides pointing in a second direction parallel to the direction of the columns, and wherein the first and second directions are opposite directions. 
     
     
         39 . The electronic device of  claim 35  wherein the substrate includes a plurality of memory cell transistors, and wherein each of the spaced apart pads is electrically coupled to a source/drain region of a respective one of the memory cell transistors. 
     
     
         40 . The electronic device of  claim 39  further comprising:
 a plurality of memory cell capacitors wherein each of the memory cell capacitors is electrically coupled to a respective one of the pads. 
 
     
     
         41 . A dynamic random access memory device comprising:
 a substrate including a plurality of memory cell transistors;   a plurality of spaced apart pads on the substrate wherein each of the spaced apart pads is electrically coupled to a source/drain region of a respective one of the memory cell transistors, wherein the plurality of pads are arranged in linear columns, and wherein a center line connecting centers of adjacent pads of different columns defines an angle of at least 60 degrees and less than 90 degrees relative to a direction of the columns; and   a plurality of memory cell capacitors wherein each of the memory cell capacitors is electrically coupled to a respective one of the pads.   
     
     
         42 . The dynamic random access memory device of  claim 41  wherein each of the pads includes first, second, third, and fourth sides, wherein the first and third sides are opposite sides that are substantially straight, and wherein the second and fourth sides are opposite sides that are curved. 
     
     
         43 . The dynamic random access memory device of  claim 42  wherein one of the second and fourth sides is concave and the other of the second and fourth sides is convex. 
     
     
         44 . The dynamic random access memory device of  claim 43  wherein pads of a first column are arranged with the convex sides pointing in a first direction parallel to the direction of the columns, wherein pads of a second column are arranged with the convex sides pointing in a second direction parallel to the direction of the columns, and wherein the first and second directions are opposite directions.