Method and system for reconfigurable channel coding

Abstract

Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder clement.

1 - 20 . (canceled) 
     
     
         21 . A reconfigurable system for providing channel coding in a wireless communication device comprising:
 a plurality of computational elements for performing a channel coding operation; and   a controller for reconfigurably controlling the plurality of computational elements to achieve channel coding operations in accordance with one of a plurality of different wireless communication standards; and   a host interface coupled to the controller, wherein the controller selects one of the plurality different wireless standards and controls the plurality of computational elements to perform the channel coding operation via the host interface.   
     
     
         22 . The reconfigurable system of  claim 21 , wherein the host interface is an interconnection network. 
     
     
         23 . The reconfigurable system of  claim 21 , wherein the host interface is a bus. 
     
     
         24 . The reconfigurable system of  claim 21 , wherein the controller is a processor. 
     
     
         25 . The reconfigurable system of  claim 21 , wherein the controller is a finite state machine. 
     
     
         26 . The reconfigurable system of  claim 21 , wherein the controller controls the plurality of computational elements via configuration information to control the functionality of the computational elements via interconnection between the computational elements. 
     
     
         27 . The reconfigurable system of  claim 26 , further comprising a configuration register storing the configuration information from the controller. 
     
     
         28 . The reconfigurable system of  claim 21  wherein each of the plurality of computational elements includes a memory storing instructions for execute commands for the channel coding operations. 
     
     
         29 . The reconfigurable system of  claim 21  wherein the plurality of computational elements comprises a plurality of polynomial generators that include a configuration register, an AND logic circuit, and an exclusive-OR logic circuit. 
     
     
         30 . The reconfigurable system of  claim 21  wherein the plurality of computational elements further comprises a Viterbi decoder element. 
     
     
         31 . The reconfigurable system of  claim 30  wherein the Viterbi decoder element further comprises a coupled configuration of a counter, a codeword and punctures look-up table, a register, recode logic, an address generator, path metrics memory, state registers, plus/minus adjusters, adders, a selector, and a comparator. 
     
     
         32 . A method for providing channel coding in a wireless communication device comprising:
 selecting one of a plurality of wireless communication standards via a controller; and   configuring a plurality of computational elements via a host interface controlled by a controller to perform a channel coding operation in accordance with the selected wireless communication standard.   
     
     
         33 . The method of  claim 32 , wherein the host interface is an interconnection network. 
     
     
         34 . The method of  claim 32 , wherein the host interface is a bus. 
     
     
         35 . The method of  claim 32 , wherein the controller is a processor. 
     
     
         36 . The method of  claim 32 , wherein the controller is a finite state machine. 
     
     
         37 . The method of  claim 32 , wherein the plurality of computational elements is controlled by configuration information to control the functionality of the computational elements via interconnection between the computational elements. 
     
     
         38 . The method of  claim 37 , further comprising, storing the configuration information in a register. 
     
     
         39 . The method of  claim 32  wherein each of the plurality of computational elements includes a memory storing instructions for execute commands for the channel coding operations. 
     
     
         40 . The method of  claim 32  wherein the plurality of computational elements further comprises a Viterbi decoder element.