Methods of fabricating a semiconductor device including fine patterns

Abstract

Methods of fabricating a semiconductor device are provided. The method includes forming active lines in a semiconductor substrate, forming contact lines generally crossing over the active lines, forming line-shaped etch mask patterns generally crossing over the active lines and the contact lines, etching the contact lines exposed by the line-shaped etch mask patterns to form contact separation grooves and to form contact patterns generally remaining at intersections between the line-shaped etch mask patterns and the active lines, etching the active lines exposed by the contact separation grooves to form active separation grooves that generally divide each of the active lines into a plurality of active patterns, forming gates that substantially intersect the active patterns, and forming bit lines electrically connected to the contact patterns.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor device, the method comprising:
 forming a first isolation layer in a semiconductor substrate to define active lines;   forming pseudo contact lines generally crossing over the active lines and a first interlayer insulation layer substantially filling spaces between the pseudo contact lines;   forming line-shaped etch mask patterns generally crossing over the active lines and the pseudo contact lines;   etching the pseudo contact lines exposed by the line-shaped etch mask patterns to form contact separation grooves and to form pseudo contact patterns generally remaining at intersections between the line-shaped etch mask patterns and the active lines;   etching the active lines exposed by the contact separation grooves to form active separation grooves that generally divide each of the active lines into a plurality of active patterns;   forming a third isolation layer substantially filling the active separation grooves;   forming gates that substantially intersect the active patterns;   removing the pseudo contact patterns to form contact holes;   forming contact patterns substantially filling the contact holes; and   forming bit lines connected to the contact patterns.   
     
     
         2 . The method of  claim 1 , wherein forming the pseudo contact lines includes:
 forming a first interlayer insulation layer substantially on the substrate including the first isolation layer;   etching the first interlayer insulation layer to form line-shaped contact grooves; and   filling the line-shaped contact grooves with a different insulation layer from the first interlayer insulation layer.   
     
     
         3 . The method of  claim 1 :
 wherein the first interlayer insulation layer is formed to include a silicon nitride layer and the pseudo contact lines are formed to include a silicon oxide layer; and   wherein the line-shaped etch mask patterns are formed to include an amorphous carbon layer different from the first interlayer insulation layer.   
     
     
         4 . The method of  claim 1 , further comprising forming spacers generally on sidewalls of the contact separation grooves after formation of the contact separation grooves,
 wherein the active separation grooves are formed to be self-aligned with the spacers and the first isolation layer exposed by the contact separation grooves.   
     
     
         5 . The method of  claim 4 , wherein the spacers are formed to include substantially the same material as the first isolation layer. 
     
     
         6 . The method of  claim 1 , wherein forming the third isolation layer includes:
 forming a silicon nitride layer substantially filling the active separation grooves and the contact separation grooves; and   planarizing the silicon nitride layer to substantially expose top surfaces of the pseudo contact patterns.   
     
     
         7 . The method of  claim 1 , wherein forming the contact patterns is followed by:
 recessing the first interlayer insulation layer and the third isolation layer to substantially expose sidewalls of the contact patterns; and   filling spaces between the exposed sidewalls of the contact patterns with a second interlayer insulation layer including a different material from the third isolation layer.   
     
     
         8 . The method of  claim 7 , wherein the second interlayer insulation layer is formed to include a silicon oxide layer. 
     
     
         9 . The method of  claim 1 , wherein forming the gates includes:
 etching the first interlayer insulation layer and the active patterns to form generally line-shaped buried gate grooves substantially intersecting the active patterns;   forming a buried gate layer substantially filling the buried gate grooves;   recessing the buried gate layer to form buried gates in respective buried gate grooves and to provide sealing grooves substantially on respective buried gates; and   forming sealing layers substantially in respective sealing grooves.   
     
     
         10 . A method of fabricating a semiconductor device, the method comprising:
 forming a first isolation layer in a semiconductor substrate to define cell active lines in a cell region of the semiconductor substrate and to define a peripheral active region in a peripheral circuit region of the semiconductor substrate;   forming pseudo contact lines that generally cross over the cell active lines and a first interlayer insulation layer that substantially fills spaces between the pseudo contact lines and substantially covers the peripheral circuit region;   forming line-shaped etch mask patterns generally crossing over the cell active lines and generally crossing over the pseudo contact lines in the cell region;   etching the pseudo contact lines exposed by the line-shaped etch mask patterns to form contact separation grooves and to form pseudo contact patterns remaining at intersections substantially between the line-shaped etch mask patterns and the cell active lines;   etching the cell active lines exposed by the contact separation grooves to form active separation grooves that generally divide each of the cell active lines into a plurality of cell active patterns;   forming a third isolation layer filling the active separation grooves;   forming buried gates that substantially intersect the cell active patterns;   selectively removing the pseudo contact patterns to form contact holes;   forming contact patterns substantially filling the contact holes;   selectively removing the first interlayer insulation layer in the peripheral circuit region to substantially expose the peripheral active region;   forming a first peripheral gate layer on the peripheral circuit region including the exposed peripheral active region;   forming a bit line layer electrically connected to the contact patterns on an entire surface of the substrate including the first peripheral gate layer; and   patterning the bit line layer and the first peripheral gate layer to form bit lines connected to the contact patterns in the cell region and to form a peripheral gate including a first peripheral gate and a second peripheral gate in the peripheral circuit region,   wherein the first peripheral gate is a portion of the first peripheral gate layer and the second peripheral gate is a portion of the bit line layer.