Input configuration for analog to digital converter

Abstract

A circuit comprising an input, two or more sampling capacitors, means for connecting each sampling capacitor to said input, means for discharging the sampling capacitors to a given voltage in a reset phase, means to use the voltage across the sampling capacitor for further processing in a hold phase, operating the two sampling capacitors in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in hold phase.

1 . A circuit comprising:
 an input; and   at least two sampling capacitors arranged in at least two different channels, each sampling capacitor being coupled to the input when in a sampling phase;   the sampling capacitors each having a reset phase to provide a given voltage received by the input during the sampling phase, a hold phase for further processing of the given voltage, and an anti-phase where the reset phase and sampling phase of one channel are performed when the reset phase and sampling phase of the other channel are in a hold phase or idle.   
     
     
         2 . The circuit according to  claim 1  wherein the circuit comprises a first stage of a pipelined ADC. 
     
     
         3 . The circuit according to  claim 1  wherein the circuit comprises part of a sample-and-hold amplifier. 
     
     
         4 . The circuit according to  claim 1  wherein the circuit comprises part of a track-and-hold amplifier. 
     
     
         5 . The circuit according to  claim 1  wherein the circuit comprises part of an input stage of an ADC. 
     
     
         6 . The circuit according to  claim 1  further comprising a differential configuration. 
     
     
         7 . A circuit comprising:
 an input;   at least two sampling capacitors arranged two different channels, the sampling capacitors coupled to the input in a sampling phase, the sampling capacitors also having a reset phase to provide a given voltage obtained in the sampling phase;   an amplifier comprising one input stage per sampling capacitor and a common output stage, wherein the sampling capacitors anti-phase with respect to each other such that the reset phase and sampling phase of one channel are performed when the other channel is in a hold phase or idle.   
     
     
         8 . The circuit according to  claim 7  wherein the circuit comprises a first stage of a pipelined ADC. 
     
     
         9 . The circuit according to  claim 7  where the circuit comprises part of a sample-and-hold amplifier. 
     
     
         10 . The circuit according to  claim 7  where the circuit comprises part of a track-and-hold amplifier. 
     
     
         11 . The circuit according to  claim 7  wherein the circuit comprises part of an input stage of an ADC. 
     
     
         12 . The circuit according to  claim 7  further comprising a differential configuration.