Image forming apparatus, chip, and chip package

Abstract

An image forming apparatus including an engine unit to perform an image forming operation, and a board unit to control the engine unit. The board unit includes at least one chip package that includes a chip. The chip includes first pads to transmit a first type of signal, a second pad to transmit a second type of signal, and a third pad interposed between the first and second pads, to reduce cross-talk between the first and second types of signals.

What is claimed is:  
     
         1 . An image forming apparatus comprising,
 an engine unit to form an image, and   a board unit comprising a chip package, to control the engine unit, the chip package comprising:   a chip;   first pads disposed on the chip, to transmit a first type of signal;   a second pad disposed on the chip, to transmit a second type of signal; and   a third pad disposed on the chip between the first pads and the second pad, to reduce cross-talk between the first and second types of signals.   
     
     
         2 . The image forming apparatus as claimed in  claim 1 , wherein the chip package further comprises:
 a fourth pad disposed on the chip, to transmit a third signal; and   a fifth pad disposed on the chip between the second pad and the fourth pad, to reduce cross-talk between the second and third types of signals.   
     
     
         3 . The image forming apparatus as claimed in  claim 1 , wherein the first, second, and third pads are linearly arranged on the chip. 
     
     
         4 . The image forming apparatus as claimed in  claim 1 , wherein the chip package further comprises:
 a substrate to support the chip; a packaging unit to encase the chip on the substrate; bonding fingers disposed on the substrate;   bonding wires to electrically connect the bonding fingers to the first, second, and third pads;   via holes vertically penetrating through the substrate; and   connectors to electrically connect the bonding fingers and the via holes.   
     
     
         5 . The image forming apparatus as claimed in  claim 4 , wherein the chip package further comprises a ground layer embedded in the substrate, under the bonding wires. 
     
     
         6 . The image forming apparatus as claimed in  claim 1 , wherein the third pad is a ground pad to transmit a fixed electric potential to the chip. 
     
     
         7 . The image forming apparatus as claimed in  claim 1 , wherein the first and second types of signals are different ones selected from data signals, address signals, and control signals. 
     
     
         8 . A chip comprising: first pads to transmit a first type of signal;
 a second pad to transmit a second type of signal; and   a third pad interposed between the first pads and the second pad, to reduce cross-talk between the first and second types of signals.   
     
     
         9 . The chip as claimed in  claim 8 , further comprising:
 a fourth pad to transmit a third type of signal; and   a fifth pad disposed between the third pad and the fourth pad, to reduce cross-talk between the second and third types of signals.   
     
     
         10 . The chip as claimed in  claim 8 , wherein the first, second, and third pads are linearly arranged on the chip. 
     
     
         11 . The chip as claimed in  claim 8 , wherein the third pad is a ground pad to transmit a fixed electric potential to the chip. 
     
     
         12 . The chip as claimed in  claim 8 , wherein the first and second signals are different ones selected from data signals, address signals, and control signals. 
     
     
         13 . A chip package comprising, a substrate, and a chip mounted on the substrate, comprising:
 first pads to transmit a first type of signal;   a second pad to transmit a second type of signal; and   a third pad interposed between the first and second pads, to reduce cross-talk between the first and second types of signals.   
     
     
         14 . The chip package as claimed in  claim 13 , wherein the chip further comprises: a fourth pad to transmit a third type of signal; and a fifth pad disposed between the third and fourth pads, to reduce cross-talk between the second and third types of signals. 
     
     
         15 . The chip package as claimed in  claim 13 , wherein the first, second, and third pads are linearly arranged on the chip. 
     
     
         16 . The chip package as claimed in  claim 13 , further comprising:
 a packaging unit to encase the chip on the substrate;   bonding fingers disposed on the substrate;   bonding wires to electrically connect the bonding fingers to the first, second, and third pads; and   connectors to electrically connect the bonding fingers to via holes that extend through the substrate.   
     
     
         17 . The chip package as claimed in  claim 16 , further comprising a ground layer embedded in the substrate, under the bonding wires. 
     
     
         18 . The chip package as claimed in  claim 13 , wherein the third pad is a ground pad to transmit a fixed electric potential to the chip. 
     
     
         19 . The chip package as claimed in  claim 13 , wherein the first and second types of signals are different ones selected from data signals, address signals, and control signals.