Semiconductor substrate suitable for the realization of electronic and/or optoelectronic devices and relative manufacturing process

Abstract

A semiconductive substrate ( 1 ) is described that is suitable for realising electronic and/or optoelectronic devices of the type comprising at least one substrate ( 3 ), in particular of single crystal silicon, and an overlying layer of single crystal silicon ( 5 ). Advantageously, according to the invention, the semiconductive substrate ( 1 ) comprises at least one functional coupling layer ( 10 ) suitable for reducing the defects linked to the differences in the materials used. In particular, the functional coupling layer 10 comprises a corrugated portion ( 6 ) made in the layer of single crystal silicon ( 5 ) and suitable for reducing the defects linked to the differences in lattice constant of such materials used. Alternatively, the functional coupling layer ( 10 ) comprises a porous layer ( 4 ) arranged between the substrate of single crystal silicon ( 3 ) and the layer of single crystal silicon ( 5 ) and suitable for reducing the stress caused by the differences between the thermal expansion coefficients of the materials used. A manufacturing process of such a semiconductive substrate is also described.

1 . A manufacturing process of a semiconductive substrate hetero-growing a semiconductive material that has a different lattice constant from that of a single crystal silicon for realizing electronic and/or optoelectronic devices which comprise said semiconductive substrate, the method comprising the steps of:
 forming a single crystal silicon substrate;   epitaxially growing a layer of single crystal silicon above said single crystal silicon substrate;   realizing a functional coupling layer above said single crystal silicon substrate, wherein said step of realizing a functional coupling layer comprises a step of defining a plurality of microstructures shaped like inverse pyramids having a tip in said layer of single crystal silicon; and   epitaxially growing a surface layer above the structure obtained with the above sequence of steps;   wherein said step of realizing a functional coupling layer comprises a step of realizing a corrugated portion of said semiconductive substrate, said corrugated portion having the function of a functional coupling layer and wherein said step of realizing said corrugated portion comprises a step of defining a plurality of microstructures in said layer of single crystal silicon wherein said definition step realizes said plurality of microstructures shaped like an inverse pyramid, the inverse pyramids being formed closely adjacent to one another.   
     
     
         2 . The manufacturing process of a semiconductive substrate according to  claim 1 , wherein said definition step realizes said plurality of microstructures shaped like a rectilinear pyramid with a square base formed by the planes of the family 111 arranged symmetrically around a central axis having its centre coinciding with a centre of symmetry of a base of said rectilinear pyramid. 
     
     
         3 . The manufacturing process of a semiconductive substrate according to  claim 1 , wherein said step of realizing a functional coupling layer comprises a step of formation of a porous layer above said substrate of single crystal silicon, said porous layer having the function of a functional coupling layer. 
     
     
         4 . The manufacturing process of a semiconductive substrate according to  claim 3 , wherein said surface layer is made above said porous layer. 
     
     
         5 . The manufacturing process of a semiconductive substrate according to  claim 1 , wherein said semiconductive substrate is made to further comprise a silicon buffer layer made between said functional coupling layer and said surface layer. 
     
     
         6 . The manufacturing process of a semiconductive substrate according to  claim 1 , wherein said semiconductive substrate it made to have minimum feature size dimensions in the order of about 100 μm. 
     
     
         7 . The manufacturing process of a semiconductive substrate according to  claim 11 , wherein said the bases and the faces of said inverse pyramids are made to have dimensions of the order of 0.1 to 10 μm in length. 
     
     
         8 . The manufacturing process of a semiconductive substrate according to  claim 1 , wherein said the bases and the faces of said inverse pyramids are made to have dimensions of around 1 μm. 
     
     
         9 . The manufacturing process of a semiconductive substrate according to  claim 1 , wherein the distance between said adjacent inverse pyramids is made to be of the order of 0 to 50% of the length of the base of the inverse pyramid. 
     
     
         10 . The manufacturing process of a semiconductive substrate according to  claim 1 , wherein the distance between said adjacent inverse pyramids is made to be of the order of 0 to 20% of the length of the base of the inverse pyramid. 
     
     
         11 . The manufacturing process of a semiconductive substrate according to  claim 1 , wherein the distance between said adjacent inverse pyramids is made to be of the order of 0 to 10% of the length of the base of the inverse pyramid. 
     
     
         12 . The manufacturing process of a semiconductive substrate according to  claim 1 , wherein said adjacent pyramids are made to be consecutive, without interruption. 
     
     
         13 . The manufacturing process of a semiconductive substrate according to  claim 1 , wherein the angle of the tip of the inverse pyramid is made to be comprised between 30 and 60°.