High density interconnect device and method

Abstract

Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

1 . A system comprising;
 a first die having a first die edge and first die surface, the first die comprising:
 a first die high density interconnect located adjacent to the first die edge on the first surface, the first die high density interconnect having a first bump pitch; 
 a first die connection region located on the first die surface, the first die connection region having a second bump pitch; and 
 a power connection region located centrally on the first die surface; and 
   a second die having a second die edge and a second die surface, the second die comprising:
 a second die high density interconnect located adjacent to the second die edge on the second die surface, the second die high density interconnect having the first bump pitch; and 
 a second die connection region located on the second die surface, the second die connection region having a third bump pitch; and 
   a bridge having a plurality of high density interconnects having the first bump pitch, one of the plurality of high density interconnects connected to the first die high density interconnect and another of the plurality of high density interconnects connected to the second die high density interconnect.   
     
     
         2 . The system of  claim 1 , wherein the first bump pitch is from about 30 μm to about 90 μm. 
     
     
         3 . The system of  claim 1 , wherein the second bump pitch is no tighter than about 60 μm. 
     
     
         4 . The system of claim I wherein the second die connection region comprises power connections. 
     
     
         5 . The system of  claim 1  wherein the first bump pitch is smaller than the second bump pitch, and the first bump pitch is smaller than the third bump pitch. 
     
     
         6 . The system of  claim 1 , wherein the second bump pitch is about equal to the third bump pitch. 
     
     
         7 . The system of  claim 1 , wherein the first die is a System On Chip (SOC) die, and the second die is a memory die. 
     
     
         8 . A microelectronic die comprising;
 a high density interconnect located adjacent to a. first edge on a first surface, the high density interconnect having a first bump pitch from about 30 μm to about 90 μm;   a connection region located adjacent to a second edge on the first surface, the connection region having a second bump pitch no tighter than about 60 μm.   
     
     
         9 . The die of  claim 8 , further comprising a power connection region located on the first surface interior to the high density interconnect and the connection region. 
     
     
         10 . The die of  claim 8 , wherein the connection region comprises power connections. 
     
     
         11 . The die of  claim 8 , wherein the connection region comprises input/output connections. 
     
     
         12 . The die of  claim 9 , wherein the die is a System On Chip (SCLC) die. 
     
     
         13 . The die of  claim 10 , wherein the die is a memory die. 
     
     
         14 . The die of  claim 8 , wherein the second bump pitch is from about 250 μm to about 400 μm. 
     
     
         15 . A method, comprising:
 providing an interconnecting bridge having a plurality of high density interconnects with a first bump pitch from about 30 μm to about 90 μm;   providing a first die having a first die high density interconnect with the first bump pitch located adjacent to a first die edge and having a first die connection region with a second bump pitch greater than the first bump pitch;   providing a second die having a second die high density interconnect with the first bump pitch located adjacent to a second die edge and having a second die connection region with a third bump pitch greater than the first bump pitch;   connecting the first die and the second die by connecting one of the high density interconnects of the interconnecting bridge to the first die high density interconnect and connecting the another of the high density interconnects of the interconnecting bridge to the second die high density interconnect; and   connecting the interconnected first die and second die to a circuit board by connecting the first die connection region to the circuit board and connecting the second die connecting region to the circuit board.   
     
     
         16 . The method of  claim 15 , wherein the first die is a System On Chip (SOC) die, and the second die is a memory die. 
     
     
         17 . The method of  claim 15 , wherein a solder temperature hierarchy is maintained such that solder joints of already bonded interfaces do not melt when later solder joints are made. 
     
     
         18 . The method of  claim 15  wherein a first set of bumps is attached by other than solder connection mechanism and a second set of bumps is attached by a solder mechanism, and wherein a temperature hierarchy is maintained so that already bonded interfaces do not melt when later solder joints are made. 
     
     
         19 . The method of  claim 15 , wherein the circuit board has a recess to receive the interconnecting bridge when the interconnected first die and second die are connected to the circuit board. 
     
     
         20 . The method of  claim 15 , wherein the circuit board has a hole to receive the interconnecting bridge when the interconnected first die and second die are connected to the circuit board.