Complementary gallium nitride integrated circuits and methods of their fabrication

Abstract

An embodiment of a complementary GaN integrated circuit includes a GaN layer with a first bandgap. A second layer with a second bandgap is formed on the GaN layer, resulting in a 2DEG in a contact region between the GaN layer and the second layer. The second layer has a relatively thin portion and a relatively thick portion. A third layer is formed over the relatively thick portion of the second layer. The third layer has a third bandgap that is different from the second bandgap, resulting in a 2DHG in a contact region between the second layer and the third layer. A transistor of a first conductivity type includes the 2DHG, the relatively thick portion of the second layer, and the third layer, and a transistor of a second conductivity type includes the 2DEG and the relatively thin portion of the second layer.

What is claimed is: 
     
         1 . A monolithic integrated circuit comprising:
 a gallium nitride (GaN) layer having a top surface and a first bandgap;   a second layer formed over the top surface of the GaN layer and having a first portion and a second portion, wherein the second layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the second layer, and wherein the first portion of the second layer is formed over a first region of the GaN layer, and the second portion of the second layer is formed over a second region of the GaN layer; and   a third layer formed over the second portion of the second layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second layer and the third layer.   
     
     
         2 . The monolithic integrated circuit of  claim 1 , further comprising:
 first and second current carrying contacts formed over the first portion of the second layer and the first region of the GaN layer;   a first channel control contact formed over the first portion of the second layer and the first region of the GaN layer and between the first and second current carrying contacts, wherein the first portion of the second layer, the 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type;   third and fourth current carrying contacts formed over the third layer, the second portion of the second layer, and the second region of the GaN layer; and   a second channel control contact formed over the third layer, the second portion of the second layer, and the second region of the GaN layer and between the third and fourth current carrying contacts, wherein the third layer, the second portion of the second layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type.   
     
     
         3 . The monolithic integrated circuit of  claim 2 , further comprising:
 an isolation structure between the first transistor and the second transistor, wherein the isolation structure is selected from an isolation mesa, an implant region, and implant well, and a trench isolation structure.   
     
     
         4 . The monolithic integrated circuit of  claim 1 , wherein the second layer is formed from a material selected from an aluminum gallium nitride (AlGaN) alloy, an indium aluminum nitride (InAlN) alloy, and an indium gallium nitride (InGaN) alloy. 
     
     
         5 . The monolithic integrated circuit of  claim 1 , wherein the second layer is formed from an aluminum gallium nitride (AlGaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent. 
     
     
         6 . The monolithic integrated circuit of  claim 1 , wherein the first portion of the second layer has a first thickness, and the second portion of the second layer has a second thickness that is greater than the first thickness. 
     
     
         7 . The monolithic integrated circuit of  claim 6 , wherein the first thickness of the first portion of the second layer is in a range of 15 nanometers to 30 nanometers. 
     
     
         8 . The monolithic integrated circuit of  claim 6 , wherein the second thickness of the second portion of the second layer is in a range of 40 nanometers to 100 nanometers. 
     
     
         9 . The monolithic integrated circuit of  claim 1 , wherein the 2DEG is present in a contact region between the first portion of the second layer and the GaN layer, and the 2DEG is suppressed in a contact region between the second portion of the second layer and the GaN layer. 
     
     
         10 . The monolithic integrated circuit of  claim 1 , wherein the 2DEG is present in a contact region between the first portion of the second layer and the GaN layer, and also is present in a contact region between the second portion of the second layer and the GaN layer. 
     
     
         11 . The monolithic integrated circuit of  claim 1 , wherein the third layer includes a semiconductor material doped with a p-type dopant. 
     
     
         12 . The monolithic integrated circuit of  claim 1 , wherein the third layer has a thickness in a range of 10 nm to 30 nm. 
     
     
         13 . An electronic circuit that includes a monolithic integrated circuit comprising:
 a gallium nitride (GaN) layer having a top surface and a first bandgap;   a first transistor of a first conductivity type formed over a first region of the top surface of the GaN layer, wherein the first transistor includes:
 a first portion of a second layer, wherein the second layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first portion of the second layer, 
 first and second current carrying contacts formed over the first portion of the second layer and the first region of the top surface of the GaN layer, and 
 a first channel control contact formed over the first portion of the second layer and the first region of the top surface of the GaN layer and between the first and second current carrying contacts; and 
   a second transistor of a second conductivity type formed over a second region of the top surface of the GaN layer, wherein the second transistor includes:
 a second portion of the second layer, 
 a third layer formed over the second portion of the second layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second layer and the third layer, 
 third and fourth current carrying contacts formed over the third layer, the second portion of the second layer, and the second region of the top surface of the GaN layer, and 
 a second channel control contact formed over the third layer, the second portion of the second layer, and the second region of the top surface of the GaN layer and between the third and fourth current carrying contacts. 
   
     
     
         14 . The electronic circuit of  claim 13 , wherein the electronic circuit is configured as an inverter, and the electronic circuit further comprises:
 a positive input terminal coupled to the first current carrying terminal of the first transistor, wherein the positive input terminal is configured to receive a first voltage from a voltage source;   a negative input terminal coupled to the fourth current carrying terminal of the second transistor, wherein the negative input terminal is configured to receive a second voltage from the voltage source;   a first transistor control terminal coupled to the first channel control contact of the first transistor, wherein the first transistor control terminal is configured to receive a first switch control signal from a controller;   a second transistor control terminal coupled to the second channel control contact of the second transistor, wherein the first transistor control terminal is configured to receive a second switch control signal from a controller;   a first diode having a first cathode and a first anode, wherein the first cathode is coupled to the first current carrying contact of the first transistor, and the first anode is coupled to the second current carrying contact of the first transistor;   a second diode having a second cathode and a second anode, wherein the second cathode is coupled to the third current carrying contact of the second transistor, and the second anode is coupled to the fourth current carrying contact of the second transistor; and   an output terminal coupled to the second current carrying contact and the third current carrying contact, wherein the output terminal is configured to provide an AC signal to a load.   
     
     
         15 . The electronic circuit of  claim 13 , wherein the electronic circuit is configured as a push-pull output, and the electronic circuit further comprises:
 a comparator having a first input, a second input, and an output, wherein the output is coupled to the first and second channel control contacts of the first and second transistors;   an input terminal coupled to the first input of the comparator;   a first power supply terminal coupled to the first current carrying terminal of the first transistor;   a second power supply terminal coupled to the fourth current carrying terminal of the second transistor; and   an output terminal coupled to the second input of the comparator, wherein the second current carrying terminal of the first transistor and the third current carrying terminal of the second transistor also are coupled to the output terminal.   
     
     
         16 . The electronic circuit of  claim 13 , wherein the electronic circuit is configured as a compound transistor, and the electronic circuit further comprises:
 an input terminal coupled to the channel control contact of the first transistor, wherein the first current carrying terminal of the first transistor is coupled to the channel control contact of the second transistor;   a source terminal coupled to the third current carrying terminal of the second transistor; and   a drain terminal coupled to the second current carrying terminal of the first transistor and to the fourth current carrying terminal of the second transistor.   
     
     
         17 . A method of fabricating a monolithic integrated circuit, the method comprising the steps of:
 providing a first gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap;   forming a second layer over a top surface of the GaN layer, wherein the second layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the second layer, wherein the second layer has a first portion formed over a first region of the top surface of the GaN layer, and a second portion formed over a second region of the top surface of the GaN layer; and   forming a third layer over the second portion of the second layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second layer and the third layer.   
     
     
         18 . The method of  claim 17 , wherein forming the second layer comprises:
 forming a first sub-layer over the first region and the second region, wherein the first sub-layer has a first thickness; and   forming a second sub-layer over a portion of the first sub-layer that is above the second region of the GaN layer, but not over a portion of the first sub-layer that is above the first region of the GaN layer, wherein a combination of the first and second sub-layers over the second region of the GaN layer has a second thickness that is greater than the first thickness.   
     
     
         19 . The method of  claim 18 , further comprising:
 before forming the third layer, suppressing the 2DEG in a contact region between the second region of the GaN layer and the second layer.   
     
     
         20 . The method of  claim 17 , further comprising:
 forming first and second current carrying contacts over the first portion of the second layer and the first region of the top surface of the GaN layer;   forming a first channel control contact over the first portion of the second layer and the first region of the top surface of the GaN layer and between the first and second current carrying contacts, wherein the first portion of the second layer, the 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type;   forming third and fourth current carrying contacts over the third layer, the second portion of the second layer, and the second region of the top surface of the GaN layer; and   forming a second channel control contact over the third layer, the second portion of the second layer, and the second region of the top surface of the GaN layer and between the third and fourth current carrying contacts, wherein the third layer, the second portion of the second layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type.