Adc with enhanced and/or adjustable accuracy

Abstract

An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.

1 . An analog-to-digital-converter comprising
 an input signal connector   an output signal port   two or more sub-ADCs   and a digital signal processing block, whereas the result from each sub-ADC is used by the digital signal processing block to output data with increased performance.   
     
     
         2 . An analog-to-digital-converter according to  claim 1  where the analog input signal is passed through separate blocks prior to being applied at the input of each sub-ADC. 
     
     
         3 . An analog-to-digital-converter comprising
 an input signal connector   an output signal port   two or more sub-ADCs   means to enable and disable the functionality of each sub-ADC individually   and a digital signal processing block, whereas the result from each sub-ADC is used by the digital signal processing block to output data with increased performance, and ability to select the number of sub-ADCs used to generate the output data thereby adjusting the total performance   
     
     
         4 . An analog-to-digital-converter according to  claim 3  where the analog input signal is passed through separate blocks prior to being applied at the input of each sub-ADC. 
     
     
         5 . An analog-to-digital-converter comprising
 an input signal connector   an output signal port   two or more sub-ADCs   means to enable and disable the functionality of each sub-ADC individually   and a digital signal processing block, whereas the sampling time of each sub-ADC is skewed such that their sampling times are distributed across the ADC sampling period, whereas the result from each sub-ADC is used by the digital signal processing block to output data with increased performance.   
     
     
         6 . An analog-to-digital-converter according to  claim 5  where the analog input signal is passed through separate blocks prior to being applied at the input of each sub-ADC.