Auto-select algorithm for a high-definition multimedia interface switch

Abstract

A multimedia device is described. The multimedia device includes a multiplexer. The multimedia device also includes a plurality of high-definition interface inputs coupled with the multiplexer and an output coupled with the multiplexer. Moreover, the multimedia device includes a processor coupled with the multiplexer to configure the multiplexer to provide one of the plurality of high definition multimedia interface inputs to the output based on the detection of a clock signal on one of the plurality of high-definition multimedia interface inputs. Furthermore, methods related to embodiments of a multimedia device are described herein.

What is claimed: 
     
         1 . A multimedia device comprising:
 a three-state virtual multiplexer configured to switch high-definition multimedia interface signals received at a plurality of inputs of the three-state virtual multiplexer;   a plurality of receivers, each receiver having a dedicated output coupled with one of the plurality of inputs of the three-state virtual multiplexer, the three-state virtual multiplexer operative to enable only one of the outputs of one of the plurality of receivers at a time;   an output coupled with the three-state virtual multiplexer;   a processor coupled with the three-state virtual multiplexer, the processor configured to monitor the plurality of inputs to detect a clock signal, and further configured to cause the three-state virtual multiplexer to automatically switch the output from a first of the plurality of inputs to a second of the plurality of inputs if the clock signal is detected on the first of the plurality of inputs;   a hot plug signal multiplexer coupled with the processor and the plurality of inputs; and   a low-speed communications channel multiplexer coupled with the processor, the hot plug signal multiplexer, and the plurality of inputs.   
     
     
         2 . The multimedia device of  claim 1  wherein, the three-state virtual multiplexer is coupled with the output through a transmitter. 
     
     
         3 . The multimedia device of  claim 1  wherein, the output is one of a plurality of outputs. 
     
     
         4 . The multimedia device of  claim 1  wherein, the processor is coupled with the clock signal of one of the plurality of inputs through a clock divide circuit for detection of a clock signal on one of the plurality inputs. 
     
     
         5 . The multimedia device of  claim 1  wherein, the processor is coupled with an analog circuit used to detect the clock signal on one of the plurality of inputs. 
     
     
         6 . The multimedia device of  claim 1  wherein, the processor coupled with the multiplexer to configure the three-state virtual multiplexer to provide one of the plurality of inputs to the output based on the detection of the clock signal on one of the plurality of inputs and detection of a voltage signal present on one of the plurality of inputs. 
     
     
         7 . The multimedia device of  claim 2  wherein, the processor is coupled with a clock detect signal on each of the receivers to detect the clock signal on one of the plurality of inputs. 
     
     
         8 . The multimedia device of  claim 2  wherein, the processor enables the transmitter based on the detection of the clock signal on one of the plurality of inputs. 
     
     
         9 . A multimedia device comprising:
 a three-state virtual multiplexer configured to switch high-definition multimedia interface signals received at a plurality of inputs of the three-state virtual multiplexer;   a plurality of receivers, each receiver having a dedicated output coupled with one of the plurality of inputs of the three-state virtual multiplexer, the three-state virtual multiplexer operative to enable only one of the outputs of one of the plurality of receivers at a time;   an output coupled with the three-state virtual multiplexer;   a processor coupled with the three-state virtual multiplexer to monitor the plurality of inputs and configured to automatically select one of the plurality of inputs to provide to the output if an attempt to read an address on one of the plurality of inputs is detected by the processor;   a hot plug signal multiplexer coupled with the processor and the plurality of inputs; and   a low-speed communications channel multiplexer coupled with the processor, the hot plug signal multiplexer, and the plurality of inputs.   
     
     
         10 . The multimedia device of  claim 9  wherein, the address contains extended display information data. 
     
     
         11 . The multimedia device of  claim 9  wherein, the processor is configured to drive a hot plug detect signal of the plurality of inputs to a voltage prior to detection of the attempt to read the address on one of the plurality of inputs. 
     
     
         12 . The multimedia device of  claim 11  wherein, the processor drives the hot plug detect signal of each plurality of inputs one by one until the processor detects the attempt to read the address on one of the plurality of inputs. 
     
     
         13 . A high-definition multimedia interface switch comprising:
 a first high-definition multimedia interface receiver having a first dedicated output;   a second receiver having a second dedicated output;   an output;   a three-state virtual multiplexer coupled with the output, the three-state virtual multiplexer including a first input coupled with the first dedicated output, a second input coupled with the second dedicated output, the three-state virtual multiplexer operative to switch signals received at the first and second inputs, the three-state virtual multiplexer operative to enable only the first dedicated output or the second dedicated output at a time;   a processor coupled with the three-state virtual multiplexer to monitor the first input and the second input for the presence of a clock signal and to automatically select between the first input and the second input to provide to the output if the presence of the clock signal is detected;   a hot plug signal multiplexer coupled with the processor and the plurality of inputs; and   a low-speed communications channel multiplexer coupled with the processor, the hot plug signal multiplexer, and the plurality of inputs.   
     
     
         14 . The high-definition multimedia interface switch of  claim 13  wherein, the three-state virtual multiplexer is coupled with the output through a transmitter. 
     
     
         15 . The high-definition multimedia interface switch of  claim 13  wherein, the first input and the second input include a transition minimized differential signaling channel and the low-speed communications channel. 
     
     
         16 . The high-definition multimedia interface switch of  claim 15  wherein, the processor selects between the first input and the second input to provide to the output based on the presence of the clock signal on the transition minimized differential signaling channel and detection of an attempted read of an extended display identification data address on the low-speed communications channel on an input. 
     
     
         17 . The high-definition multimedia interface switch of  claim 15  wherein, the processor determines the presence of the clock signal on the transition minimized differential signaling channel through a clock detect signal on the first receiver or on the second receiver. 
     
     
         18 . The high-definition multimedia interface switch of  claim 17  wherein, the processor enables the transmitter upon determining the presence of the clock signal on one of the first or second inputs to provide the first or second input with the clock signal present to the output. 
     
     
         19 . The high-definition multimedia interface switch of  claim 13  wherein, the low-speed communications channel includes an address for extended display information data. 
     
     
         20 . The high-definition multimedia interface switch of  claim 19  wherein, the processor is configured to drive a hot plug detect signal of the plurality of inputs to a voltage prior to detection of an attempt to read the address on one of the plurality of inputs.