Virtualizing interrupt priority and delivery

Abstract

Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

What is claimed is: 
     
         1 . A processor comprising:
 instruction hardware to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events; and   execution hardware to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.   
     
     
         2 . The processor of  claim 1 , wherein the execution hardware is to determine the processor-priority value by computing the maximum of a highest priority virtual interrupt in-service field of a virtual machine control structure and a virtual task-priority register value. 
     
     
         3 . The processor of  claim 1 , wherein the execution hardware is also to determine whether a virtual interrupt is to be recognized by comparing a highest priority virtual interrupt-requested field of a virtual machine control structure and the first virtual processor-priority value. 
     
     
         4 . The processor of  claim 1 , wherein the execution hardware is also to respond, within the non-root mode, to an attempt by the guest software to write a task-priority value to a task-priority register by computing the maximum of the task-priority value and a highest priority virtual interrupt in-service field of a virtual machine control structure to determine a second virtual processor-priority value. 
     
     
         5 . The processor of  claim 4 , wherein the execution hardware is also to determine whether a virtual interrupt is to be recognized by comparing a highest priority virtual interrupt-requested field of a virtual machine control structure and the second virtual processor-priority value. 
     
     
         6 . The processor of  claim 1 , wherein the execution hardware is also to respond, within the non-root mode, to an attempt by the guest software to send a self-interprocessor interrupt by computing the maximum of a self-interprocessor interrupt vector and a highest priority virtual interrupt-requested field of a virtual machine control structure to determine a new highest priority virtual interrupt-requested value. 
     
     
         7 . The processor of  claim 6 , wherein the execution hardware is also to determine whether a virtual interrupt is to be recognized by comparing the new highest priority virtual interrupt-requested value and the first virtual processor-priority value. 
     
     
         8 . The processor of  claim 1 , wherein the execution hardware is also to respond, within the non-root mode, to an attempt by the guest software to write to an end-of-interrupt register by clearing a bit in a virtual copy of an in-service register, the bit corresponding to a highest priority virtual interrupt in-service field in a virtual machine structure. 
     
     
         9 . The processor of  claim 3 , wherein the execution hardware is also to determine whether delivery of virtual interrupts is masked at an instruction boundary and deliver the virtual interrupt if delivery is unmasked. 
     
     
         10 . A method comprising:
 receiving, by a processor, an instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events;   executing, by the processor, the instruction, where execution includes determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.   
     
     
         11 . The method of  claim 10 , wherein determining the processor-priority value includes computing the maximum of a highest priority virtual interrupt in-service field of a virtual machine control structure and a virtual task-priority register value. 
     
     
         12 . The method of  claim 10 , further comprising determining whether a virtual interrupt is to be recognized by comparing a highest priority virtual interrupt-requested field of a virtual machine control structure and the first virtual processor-priority value. 
     
     
         13 . The method of  claim 10 , further comprising responding, within the non-root mode, to an attempt by the guest software to write a task priority value to a task-priority register by computing the maximum of the task-priority value and a highest priority virtual interrupt in-service field of a virtual machine control structure to determine a second virtual processor-priority value. 
     
     
         14 . The method of  claim 13 , further comprising determining whether a virtual interrupt is to be recognized by comparing a highest priority virtual interrupt-requested field of a virtual machine control structure and the second virtual processor-priority value. 
     
     
         15 . The method of  claim 10 , further comprising responding, within the non-root mode, to an attempt by the guest software to send a self-interprocessor interrupt by computing the maximum of a self-interprocessor interrupt vector and a highest priority virtual interrupt-requested field of a virtual machine control structure to determine a new highest priority virtual interrupt-requested value. 
     
     
         16 . The method of  claim 15 , further comprising determining whether a virtual interrupt is to be recognized by comparing the new highest priority virtual interrupt-requested value and the first virtual processor-priority value. 
     
     
         17 . The method of  claim 10 , further comprising responding, within a non-root mode, to an attempt by the guest software to write to an end-of-interrupt register by clearing a bit in a virtual copy of an in-service register, the bit corresponding to a highest priority virtual interrupt in-service field in a virtual machine structure. 
     
     
         18 . The method of  claim 17 , further comprising determining whether delivery of virtual interrupts is masked at an instruction boundary and delivering the virtual interrupt if delivery is unmasked. 
     
     
         19 . A system comprising:
 a memory; and   a processor including
 instruction hardware to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events; and 
 execution hardware to execute the first instruction, execution of the first instruction to include determining a virtual processor-priority value and storing the first virtual processor-priority value in the memory in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller. 
   
     
     
         20 . The system of  claim 19 , wherein the execution hardware is also to determine whether a virtual interrupt is to be recognized by comparing a highest priority virtual interrupt-requested field in a virtual machine control structure in the memory and the virtual processor-priority value.