ALLOCATING LANES IN A PERIPHERAL CONNECT INTERFACE EXPRESS ('PCIe') BUS

Abstract

Allocating lanes in a Peripheral Connect Interface Express (‘PCIe’) bus, including: determining, by a lane allocation module, performance capabilities of a device coupled to the PCIe bus; and allocating, by the lane allocation module, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device.

1 . A method of allocating lanes in a Peripheral Connect Interface Express (‘PCIe’) bus, the method comprising:
 determining, by a lane allocation module, performance capabilities of a device coupled to the PCIe bus; and 
 allocating, by the lane allocation module, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device. 
 
     
     
         2 . The method of  claim 1  wherein determining performance capabilities of the device coupled to the PCIe bus further comprises determining a device type for the device coupled to the PCIe bus. 
     
     
         3 . The method of  claim 3  wherein determining a device type for the device coupled to the PCIe bus further comprises retrieving, from the device, vital product data (‘VPD’) for the device. 
     
     
         4 . The method of  claim 1  wherein determining performance capabilities of the device coupled to the PCIe bus further comprises determining one or more performance capabilities of a downstream device. 
     
     
         5 . The method of  claim 4  wherein determining one or more performance capabilities of a downstream device further comprises retrieving, from the downstream device, performance capabilities of the downstream device. 
     
     
         6 . The method of  claim 1  wherein allocating the number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device further comprises deallocating one or more lanes in the PCIe bus for use by a second device. 
     
     
         7 - 20 . (canceled)