Semiconductor devices with vertical channel structures

Abstract

Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate comprising an top surface;   a first insulating layer on the top surface of the substrate;   a ground selection gate electrode on the first insulating layer;   a second insulating layer on the ground selection gate electrode;   a channel structure contacting the substrate, extending through the first insulating layer, the ground selection gate electrode, and the second insulating layer in a first direction perpendicular to the top surface of the substrate, and comprising a channel layer, a channel contact layer, and a stepped portion; and   a gate insulating layer surrounding portions of an outer wall of the channel structure, wherein the gate insulating layer comprises a tunnel insulating layer on the channel structure, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer,   wherein the channel contact layer contacts the substrate, extends in the first direction, comprises a conductive material doped with impurities of a first impurity type, and comprises a first width in a second direction perpendicular to the first direction, and   wherein the channel layer contacts the channel contact layer, extends in the first direction, comprises a conductive material doped with impurities of the first impurity type, comprises a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and comprises a second width in the second direction different from the first width.   
     
     
         2 . The semiconductor device of  claim 1 ,
 wherein the channel layer comprises an inner surface contacting portions of an outer surface of the channel contact layer,   wherein the second width is greater than the first width, and   wherein the bottom surface of the channel layer forms a stepped portion of the channel structure.   
     
     
         3 . The semiconductor device of  claim 2 , further comprising an etch stop layer between the substrate and the first insulating layer, wherein the bottom surface of the channel layer is between top and bottom surfaces of the etch stop layer in the first direction. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the bottom surface of the channel layer contacts a top surface of the channel contact layer and wherein the second width is less than the first width. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a word line gate electrode on the second insulating layer and comprising a first semiconductor material,
 wherein the ground selection gate electrode comprises a second semiconductor material different from the first semiconductor material.   
     
     
         6 . The semiconductor device of  claim 1 , wherein the blocking insulating layer comprises a first blocking insulating layer on the charge storage layer and a second blocking insulating layer separating the first blocking insulating layer from the ground selection gate electrode. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the first and second insulating layers contact the second blocking insulating layer. 
     
     
         8 . The semiconductor device of  claim 6 , wherein the first and second insulating layers contact the first blocking insulating layer. 
     
     
         9 . The semiconductor device of  claim 6 , wherein the first and second insulating layers contact the charge storage layer. 
     
     
         10 . A semiconductor device comprising:
 a channel structure protruding a top surface of a substrate and extending in a first direction perpendicular to the top surface of the substrate; and   a ground selection line, a plurality of word lines, and a string selection line sequentially disposed on the substrate, separated from each other in the first direction, and each surrounding a respective portion of a side surface of the channel structure,   wherein the channel structure comprises a stepped portion formed in the side surface of the channel structure between the ground selection line and the top surface of the substrate.   
     
     
         11 . The semiconductor device of  claim 10 ,
 wherein a portion of the channel structure located at the same height as the ground selection line in the first direction has a first width in a second direction perpendicular to the first direction, and   wherein a portion of the channel structure located at the same height as the top surface of the substrate in the first direction has a second width, smaller than the first width, in the second direction.   
     
     
         12 . The semiconductor device of  claim 10 ,
 wherein the channel structure comprises a channel contact layer connected to the substrate and extending in the first direction, and a channel layer surrounding portions of an outer surface of the channel contact layer, and   wherein a bottom portion of the channel layer forms the stepped portion of the channel structure.   
     
     
         13 . The semiconductor device of  claim 10 , further comprising an etch stop layer disposed between the ground selection line and the substrate,
 wherein a distance between the stepped portion of the channel structure and the top surface of the substrate is less than a distance between a top surface of the etch stop layer and the top surface of the substrate.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the etch stop layer surrounds a portion of an outer surface of the channel contact layer. 
     
     
         15 . The semiconductor device of  claim 10 ,
 wherein a portion of the channel structure located at the same height as the ground selection line in the first direction has a first width in a second direction perpendicular to the first direction, and   wherein a portion of the channel structure located at the same height as the top surface of the substrate in the first direction has a second width, larger than the first width, in the second direction.   
     
     
         16 . The semiconductor device of  claim 10 ,
 wherein the channel structure comprises a channel contact layer connected to the substrate and a channel layer on the channel contact layer, and   wherein an upper portion of the channel contact layer forms the stepped portion of the channel structure.   
     
     
         17 . The semiconductor device of  claim 10 , wherein the ground selection line comprises a first material and the word line comprises a second material different from the first material. 
     
     
         18 . The semiconductor device of  claim 10 , further comprising a gate insulating layer surrounding portions of an outer surface of the channel structure and extending in the first direction. 
     
     
         19 . A semiconductor device comprising:
 a ground selection line, a plurality of word lines, and a string selection line sequentially disposed on a substrate in a first direction perpendicular to a top surface of the substrate; and   a channel structure passing through the ground selection line, the word lines, and the string selection line and contacting the substrate,   wherein the channel structure comprises a stepped portion comprising a step height in a second direction perpendicular to the first direction,   wherein the stepped portion is formed in a side wall surface of the channel structure between the ground selection line and the top surface of the substrate.   
     
     
         20 . The semiconductor device of  claim 19 ,
 wherein the channel structure has a first width in the second direction in a portion of the side wall surface of the channel structure located at a higher level than the stepped portion in the first direction, and   wherein the channel structure has a second width, larger than the first width, in the second direction in a portion of the side wall surface of the channel structure located at a lower level than the stepped portion in the first direction.