Nonvolatile memory device, method of manufacturing the nonvolatile memory device, and memory module and system including the nonvolatile memory device

Abstract

A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.

What is claimed is: 
     
         1 . A nonvolatile memory device comprising:
 a substrate;   a semiconductor channel layer protruding from the substrate;   a gate conductive layer adjacent a sidewall of the semiconductor channel layer;   a gate insulating layer between the semiconductor channel layer and the gate conductive layer; and   an insulating layer on a top and a bottom of the gate conductive layer,   wherein a gap is within the gate insulating layer and between the insulating layer and the semiconductor channel layer.   
     
     
         2 . The nonvolatile memory device of  claim 1 , wherein the gate conductive layer comprises an end comprising a dogbone shape. 
     
     
         3 . The nonvolatile memory device of  claim 1 , wherein the gate insulating layer extends between the gate conductive layer and the insulating layer. 
     
     
         4 . The nonvolatile memory device of  claim 1 , further comprising a gate separation insulating layer between the gate conductive layer and the semiconductor channel layer, wherein the gate separation insulating layer extends between the gate conductive layer and the insulating layer. 
     
     
         5 . The nonvolatile memory device of  claim 1 , wherein the insulating layer is spaced apart from the semiconductor channel layer. 
     
     
         6 . The nonvolatile memory device of  claim 1 ,
 wherein the insulating layer comprises a plurality of first insulating layers, and   wherein the device further comprises a second insulating layer on a portion of a sidewall of an uppermost one of the plurality of first insulating layers.   
     
     
         7 . The nonvolatile memory device of  claim 1 , further comprising:
 a separating insulating layer protruding from the substrate; and   a supporting insulating layer protruding from the substrate and being in a space between the semiconductor channel layer and the separating insulating layer.   
     
     
         8 . The nonvolatile memory device of  claim 7 , wherein the semiconductor channel layer defines a zigzag pattern, and the supporting insulating layer defines an inverse zigzag pattern. 
     
     
         9 . A nonvolatile memory device comprising:
 a substrate;   a semiconductor channel layer protruding from the substrate;   a gate conductive layer adjacent a sidewall of the semiconductor channel layer;   a gate insulating layer between the semiconductor channel layer and the gate conductive layer; and   an insulating layer on a top and a bottom of the gate conductive layer,   wherein the gate conductive layer comprises an end comprising a dogbone shape.   
     
     
         10 . The nonvolatile memory device of  claim 9 , wherein the gate insulating layer extends between the gate conductive layer and the insulating layer. 
     
     
         11 . The nonvolatile memory device of  claim 9 , further comprising a gate separation insulating layer between the gate conductive layer and the semiconductor channel layer, wherein the gate separation insulating layer extends between the gate conductive layer and the insulating layer. 
     
     
         12 . The nonvolatile memory device of  claim 9 , wherein the insulating layers is spaced apart from the semiconductor channel layer. 
     
     
         13 . The nonvolatile memory device of  claim 9 ,
 wherein the insulating layer comprises a plurality of first insulating layers, and   wherein the device further comprises a second insulating layer on a portion of a sidewall of an uppermost one of the plurality of first insulating layers.   
     
     
         14 . The nonvolatile memory device of  claim 9 , further comprising:
 a separating insulating layer protruding from the substrate; and   a supporting insulating layer protruding from the substrate and being in a space between the semiconductor channel layer and the separating insulating layer.   
     
     
         15 . The nonvolatile memory device of  claim 14 , wherein the semiconductor channel layer defines a zigzag pattern, and the supporting insulating layer defines an inverse zigzag pattern. 
     
     
         16 . A nonvolatile memory device comprising:
 a substrate;   a semiconductor channel layer protruding from the substrate;   a gate conductive layer adjacent a sidewall of the semiconductor channel layer;   a gate insulating layer between the semiconductor channel layer and the gate conductive layer;   an insulating layer on a top and a bottom of the gate conductive layer;   a separating insulating layer protruding from the substrate; and   a supporting insulating layer protruding from the substrate and being in a space between the semiconductor channel layer and the separating insulating layer.   
     
     
         17 . The nonvolatile memory device of  claim 16 , wherein the semiconductor channel layer defines a zigzag pattern, and the supporting insulating layer defines an inverse zigzag pattern. 
     
     
         18 . The nonvolatile memory device of  claim 16 , wherein the gate conductive layer comprises an end comprising a dogbone shape. 
     
     
         19 . The nonvolatile memory device of  claim 16 , further comprising a gate separation insulating layer between the gate conductive layer and the semiconductor channel layer, wherein the gate separation insulating layer extends between the gate conductive layer and the insulating layer. 
     
     
         20 . The nonvolatile memory device of  claim 16 ,
 wherein the insulating layer comprises a plurality of first insulating layers, and   wherein the device further comprises a second insulating layer on a portion of a sidewall of an uppermost one of the plurality of first insulating layers.