Noise and Cross-Talk Attenuation in an Audio System by Offsetting Outputs in Phase

Abstract

An amplifier may include two or more pulse-width modulators (PWMs) controlling respective sets of switches to produce an amplified version of a source signal. The clocking for the amplifier may be controlled to delay signal processing within the PWMs relative to one another in time, thereby providing an effective time offset between the absolute moment in time of the edge transition of the controlling signals to the respective sets of switches. The PWMs may include a decrementor that counts down to zero from the next PWM duty-cycle value when a new data sample is detected, beginning a new count when the next sample is present. The PWM output may correspond to the counter value, outputting a pulse when the counter value is nonzero. A “data-sample-ready” signal may be decoded from a master counter, which may be clocked based on the high speed PWM clock, and the delay mechanism may be based on adjusting the decode value to determine when the PWM should initialize to the next data sample.

We claim: 
     
         1 . A method for attenuating non-linear noise in an open-loop amplifier, the method comprising:
 receiving a source signal;   generating a first control input signal and a second control input signal from the source signal, wherein the first control input signal and the second control input signal are together representative of the source signal;   generating a first control output signal by processing the first control input signal, and generating a second control output signal by processing the second control input signal;   providing an effective timing offset between respective edge transitions of the first control output signal and the second control output signal by delaying in time said processing the first control input signal relative to said processing the second control input signal; and   generating an amplified version of the source signal by:
 controlling a first set of switches with the first control output signal; and 
 controlling a second set of switches with the second control output signal. 
   
     
     
         2 . The method of  claim 1 , wherein said delaying comprises:
 generating a first ready signal and a second ready signal; and   not processing the first control input signal until the first ready signal is asserted, and not processing the second control input signal until the second ready signal is asserted.   
     
     
         3 . The method of  claim 2 , further comprising:
 when asserting the first ready signal, asserting the first ready signal for a single cycle of a clock signal used for processing the first control input signal; and   when asserting the second ready signal, asserting the second ready signal for a single cycle of a clock signal used for processing the second control input signal.   
     
     
         4 . The method of  claim 2 ;
 wherein said generating the first ready signal comprises generating the first ready signal based on a frame counter clocked with a first clock signal also used for processing the first control input signal; and   wherein said generating the second ready signal comprises generating the second ready signal based on a frame counter clocked with a second clock signal also used for processing the second control input signal.   
     
     
         5 . The method of  claim 4 , wherein said generating the first ready signal comprises adjusting a first decode value derived from the frame counter to determine when to assert the first ready signal; and
 wherein said generating the second ready signal comprises adjusting a second decode value derived from the frame counter to determine when to assert the second ready signal.   
     
     
         6 . The method of  claim 1 ;
 wherein said processing the first control input signal comprises:
 counting down from a present value of the first control input signal; and 
 asserting the first control output signal until said counting reaches zero; and 
   wherein said processing the second control input signal comprises:
 counting down from a present value of the second control input signal; and 
 asserting the second control output signal until said counting reaches zero. 
   
     
     
         7 . An amplifier comprising:
 an input interface configured to receive a source signal;   a first set of control switches and a second set of control switches configured to produce an amplified version of the source signal;   a preprocessor configured to generate a first control input value and a second control input value based on the source signal, wherein the first control input value and the second control input value are together representative of a sample of the source signal;   driver circuitry configured to:
 generate a first control output signal by processing the first control input value; 
 generate a second control output signal by processing the second control input value; and 
 create an amplified version of the source signal by controlling a first set of switches with the first control output signal, and controlling a second set of switches with the second control output signal; and 
   delay circuitry configured to provide an effective timing offset between respective edge transitions of the first control output signal and the second control output signal by instructing the driver circuitry to delay in time the processing of the first control input value relative to the processing of the second control input value.   
     
     
         8 . The amplifier of  claim 7 , wherein the delay circuit is configured to generate a first ready signal and a second ready signal, and provide the first ready signal and the second ready signal to the driver circuitry; and
 wherein the driver circuitry is configured to not process the first control input value until the first ready signal is asserted by the delay circuitry, and not process the second control input value until the second ready signal is asserted by the delay circuitry.   
     
     
         9 . The amplifier of  claim 8 , wherein the driver circuitry is configured to process the first control input value and the second control input value according to a first clock signal;
 wherein the delay circuitry is configured to assert the first ready signal and the second ready signal for a single cycle of the first clock signal.   
     
     
         10 . The amplifier of  claim 8 , wherein the driver circuitry is configured to process the first control input value and the second control input value according to a first clock signal;
 wherein the delay circuitry comprises:
 a frame counter clocked with the first clock signal; and 
 a counter decode circuit configured to receive a count value from the frame counter and generate the first ready signal and the second ready signal according to the count value. 
   
     
     
         11 . The amplifier of  claim 10 , wherein the counter decode circuit is configured to derive a decode value from the count value, and adjust the decode value to specify when to assert the first ready signal and the second ready signal. 
     
     
         12 . The amplifier of  claim 8 , wherein the driver circuitry comprises two stages respectively configured to:
 receive the first input control value and the second input control value as respective input values;   receive the first ready signal and the second ready signal as respective count enable signals; and   generate the first control output signal and the second control output signal as respective outputs;   wherein each of the two stages is configured to:
 begin counting down from the input control value to zero when the count enable signal is asserted; 
 assert the output until zero is reached; and 
 deassert the output once zero is reaches. 
   
     
     
         13 . The amplifier of  claim 7 , wherein the driver circuitry comprises pulse-width modulation (PWM) circuitry, wherein the first control input value and the second control input value correspond to duty-cycle values, and the first control output signal and the second control output signal are PWM signals. 
     
     
         14 . The amplifier of  claim 7 , further comprising the first set of switches and the second set of switches. 
     
     
         15 . The amplifier of  claim 14 , wherein the first set of switches and the second set of switches comprise CMOS (Complementary Metal-Oxide Semiconductor) devices. 
     
     
         16 . The amplifier of  claim 7 , wherein the source signal is an audio signal. 
     
     
         17 . An amplifier comprising:
 a first processing element configured to generate a first control value and a second control value from a sampled value of a source signal;   a second processing element configured to:
 generate a first control output signal by processing the first control value; 
 generate a second control output signal by processing the second control value; and 
 create an amplified version of the source signal by controlling a first set of switches with the first control output signal, and controlling a second set of switches with the second control output signal; and 
   a third processing element configured to provide an effective timing offset between respective edge transitions of the first control output signal and the second control output signal by instructing the second processing element to delay in time the processing of the first control value relative to the processing of the second control value.   
     
     
         18 . The amplifier of  claim 17 , wherein the third processing element is configured to generate a first ready signal and a second ready signal; and
 wherein the second processing element is configured to not process the first control value until the first ready signal is asserted, and not process the second control value until the second ready signal is asserted.   
     
     
         19 . The amplifier of  claim 18 , wherein the second processing element is configured to process the first control value and the second control value according to a first clock signal;
 wherein the third processing element is configured to assert the first ready signal and the second ready signal for a single cycle of the first clock signal.   
     
     
         20 . The amplifier of  claim 18 , wherein the second processing element is configured to process the first control value and the second control value according to a first clock signal;
 wherein the third processing element comprises:
 a frame counter clocked with the first clock signal; and 
 a counter decode circuit configured to receive a count value from the frame counter and generate the first ready signal and the second ready signal according to the count value. 
   
     
     
         21 . The amplifier of  claim 20 , wherein the counter decode circuit is configured to derive a decode value from the count value, and adjust the decode value to determine a first point in time at which to assert the first ready signal, and a second point in time at which to assert the second ready signal. 
     
     
         22 . The amplifier of  claim 18 , wherein the second processing element is further configured to:
 begin a first count from the first control value to zero when the first ready signal is asserted;   begin a second count from the second control value to zero when the second ready signal is asserted;   assert the first control output signal until the first count reaches zero;   assert the second control output signal until the second count reaches zero;   deassert the first control output signal once the first count reaches zero; and   deassert the second control output signal once the second count reaches zero.   
     
     
         23 . The amplifier of  claim 17 , wherein the second processing element comprises:
 a first pulse-width modulation (PWM) circuit configured to receive the first control value which corresponds to a first duty-cycle value, and generate the first control output signal which is a PWM signal according to the first duty-cycle value; and   a second PWM circuit configured to receive the second control value which corresponds to a second duty-cycle value, and generate the second control output signal which is a PWM signal according to the second duty-cycle value.   
     
     
         24 . The amplifier of  claim 17 , further comprising the first set of switches and the second set of switches. 
     
     
         25 . The amplifier of  claim 24 , wherein the first set of switches and the second set of switches comprise CMOS (Complementary Metal-Oxide Semiconductor) devices. 
     
     
         26 . The amplifier of  claim 17 , wherein the source signal is an audio signal.