US2015064848A1PendingUtilityA1

Semiconductor device having a diamond substrate heat spreader

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Assignee: ESTIVATION PROPERTIES LLCPriority: Feb 2, 2009Filed: Oct 28, 2014Published: Mar 5, 2015
Est. expiryFeb 2, 2029(~2.6 yrs left)· nominal 20-yr term from priority
H10W 72/884H10W 72/07236H10W 72/252H10W 76/134H10W 72/012H10W 42/121H10W 40/254H01L 2224/13144H01L 2924/01032H01L 24/11H01L 2224/81801H01L 2224/13147H01L 2924/13091H01L 23/562H01L 23/3732H01L 24/81
42
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Claims

Abstract

In accordance with one or more embodiments, a semiconductor device comprises a semiconductor die having a heat region disposed on at least one portion of the semiconductor die, and a diamond substrate disposed proximate to the semiconductor die, wherein the diamond substrate is capable of dissipating heat from the diamond substrate via at least one or more bumps coupling the diamond substrate to the heat region of the semiconductor die.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method to remove heat from a side of a semiconductor substrate in which a power transistor is formed, the method comprising:
 providing a first thermal pathway for removing heat from the power transistor, wherein the first thermal pathway is in proximity to a channel region of the power transistor;   contacting the first thermal pathway with a metal contact region overlying an active area of the power transistor;   providing a second thermal pathway for removing heat from the semiconductor substrate, wherein the second thermal pathway includes at least one hard bump of a predetermined height contacting the metal contact region;   coupling the at least one hard bump to a diamond substrate for spreading heat, wherein the diamond substrate is spaced approximately the predetermined height from the semiconductor substrate; and   coupling the diamond substrate to a heat sink for removing heat from the semiconductor substrate.   
     
     
         2 . The method of  claim 1 , wherein heat generated by the power transistor is removed from the semiconductor substrate through the first thermal pathway or the second thermal pathway, or combinations thereof 
     
     
         3 . The method of  claim 1 , wherein the first thermal pathway comprises metal. 
     
     
         4 . The method of  claim 1 , further comprising forming the hard bumps of gold or gold alloy, wherein the gold is at least partially malleable for further reducing stress on the semiconductor substrate. 
     
     
         5 . The method of  claim 1 , further comprising forming the hard bumps of copper or copper alloy. 
     
     
         6 . The method of  claim 1 , wherein the diamond substrate is one of a plurality of diamond substrates in an array. 
     
     
         7 . The method of  claim 1 , further comprising attaching the diamond substrate with solder for reducing stress on the diamond substrate or the semiconductor substrate, or combinations thereof 
     
     
         8 . A method for reducing stress on a semiconductor device, the method comprising:
 providing a semiconductor substrate having first and second contact regions on a first surface and a third contact region on a second surface;   providing a diamond substrate having first and second contact regions overlying a first surface and a third contact region on a second surface, wherein the first and second contact regions of the diamond substrate are coplanar;   coupling the semiconductor substrate to the diamond substrate, wherein at least one hard bump of a predetermined height is attached to the first contact regions of the semiconductor and diamond substrates, and wherein at least one hard bump of the predetermined height is attached to the second contact regions of the semiconductor and diamond substrates; and   coupling the diamond substrate to a planar metal surface, wherein the third contact region of the diamond substrate is attached to the planar metal surface, and wherein the diamond substrate is configured to act as a stress buffer to reduce stress on the semiconductor substrate.   
     
     
         9 . The method of  claim 8 , further comprising forming the hard bumps of gold or gold alloy wherein the gold is at least partially malleable for further reducing stress on the semiconductor substrate. 
     
     
         10 . The method of  claim 8 , further comprising forming the hard bumps of copper or copper alloy. 
     
     
         11 . The method of  claim 8 , further comprising attaching the third contact region of the diamond substrate to the metal surface with gold-germanium. 
     
     
         12 . The method of  claim 8 , further comprising attaching the third contact region of the diamond substrate with solder for reducing stress on the diamond substrate or the semiconductor substrate, or combinations thereof. 
     
     
         13 . The method of  claim 8 , further comprising attaching the third contact region of the diamond substrate with a conductive epoxy for reducing stress on the diamond substrate or the semiconductor substrate, or combinations thereof 
     
     
         14 . A method comprising:
 forming first and second contact regions on a first surface of a semiconductor substrate;   forming a third contact region on a second surface of the semiconductor substrate;   forming a diamond substrate with first, second, and third contact regions, wherein the first and second contact regions of the diamond substrate are coplanar;   coupling the semiconductor substrate to the diamond substrate, wherein at least one hard bump of a predetermined height is attached to the first contact regions of the semiconductor and diamond substrates, and wherein at least one hard bump of the predetermined height is attached to the second contact regions of the semiconductor and diamond substrates; and   coupling the diamond substrate to a planar metal surface.   
     
     
         15 . The method of  claim 14 , wherein the third contact region of the diamond substrate is attached to the planar metal surface. 
     
     
         16 . The method of  claim 14 , further comprising forming the hard bumps of gold or gold alloy, wherein the gold is at least partially malleable. 
     
     
         17 . The method of  claim 14 , further comprising forming the hard bumps of copper or copper alloy. 
     
     
         18 . The method of  claim 14 , further comprising attaching the third contact region of the diamond substrate to the metal surface with gold-germanium. 
     
     
         19 . The method of  claim 14 , further comprising attaching the third contact region of the diamond substrate with solder for reducing stress on the diamond substrate or the semiconductor substrate, or combinations thereof. 
     
     
         20 . The method of  claim 14 , further comprising attaching the third contact region of the diamond substrate with a conductive epoxy for reducing stress on the diamond substrate or the semiconductor substrate, or combinations thereof

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