Semiconductor device and method for fabricating the same

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

1 . A method for fabricating semiconductor device, comprising:
 providing a substrate;   forming an interfacial layer on the substrate;   forming a high-k dielectric layer on the interfacial layer;   forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer;   performing a thermal treatment;   removing the first BBM layer; and   forming a second BBM layer on the high-k dielectric layer.   
     
     
         2 . The method of  claim 1 , further comprising performing a pre-clean before forming the interfacial layer. 
     
     
         3 . The method of  claim 1 , further comprising:
 forming a sacrificial layer on the second BBM layer;   patterning the sacrificial layer to form a dummy gate;   forming a spacer on the sidewall of the dummy gate;   forming a source/drain region in the substrate adjacent to the spacer;   forming a contact etch stop layer on the dummy gates;   forming an interlayer dielectric layer (ILD) on the contact etch stop layer; and   performing a replacement metal gate (RMG) process to form the dummy gate into metal gate.   
     
     
         4 . The method of  claim 3 , wherein the sacrificial layer comprises amorphous silicon or polysilicon. 
     
     
         5 . The method of  claim 1 , wherein the interfacial layer comprises silicon oxide. 
     
     
         6 . The method of  claim 1 , wherein the first BBM layer and the second BBM layer comprise TiN. 
     
     
         7 . The method of  claim 1 , further comprising forming a silicon layer on the first BBM layer before performing the thermal treatment. 
     
     
         8 . The method of  claim 7 , further comprising removing the silicon layer and the first BBM layer before forming the second BBM layer. 
     
     
         9 . The method of  claim 7 , wherein the silicon layer comprises amorphous silicon. 
     
     
         10 . The method of  claim 7 , wherein the thickness of the silicon layer is between 100 Angstroms to 300 Angstroms. 
     
     
         11 . The method of  claim 1 , wherein the temperature of the thermal treatment is between 700-1000° C. . 
     
     
         12 . A semiconductor device, comprising:
 a substrate;   a gate structure on the substrate, wherein the gate structure comprises:
 an interfacial layer, wherein the nitrogen concentration of the interfacial layer is less than 10 ppm; and 
 a gate on the interfacial layer; and 
   a source/drain region in the substrate adjacent to the gate structure.   
     
     
         13 . The semiconductor device of  claim 12 , further comprising a spacer around the gate structure. 
     
     
         14 . The semiconductor device of  claim 12 , wherein the gate comprises:
 a high-k dielectric layer on the interfacial layer;   a bottom barrier metal (BBM) layer on the high-k dielectric layer;   a work function layer on the BBM layer; and   a low resistance metal layer on the work function layer.   
     
     
         15 . The semiconductor device of  claim 14 , wherein the BBM layer comprises TiN. 
     
     
         16 . The semiconductor device of  claim 14 , wherein the work function layer comprises a p-type work function layer or a n-type work function layer.