Resistance change memory

Abstract

According to one embodiment, a resistance change memory includes the following structure. A memory cell includes a resistance change element and a transistor. A sense amplifier reads data stored in the memory cell. A control circuit controls the reading by the sense amplifier, and outputs a first signal to control the start of precharging of the bit line, a second signal to control a cell current running through the memory cell, and a third signal to control the start of the activation of the sense amplifier. A second word line has an interconnect structure similar to that of the first word line. A monitor circuit detects a first signal delay in the second word line, and outputs the first signal to the sense amplifier in accordance with the first signal delay.

What is claimed is: 
     
         1 . A resistance change memory comprising:
 a first memory cell comprising a first resistance change element and a first transistor, the first memory cell being connected to a bit line, the first transistor being connected to a first word line;   a sense amplifier configured to read data stored in the first memory cell;   a control circuit configured to control the reading by the sense amplifier, the control circuit outputting a first signal to control the start of precharging of the bit line, a second signal to control a cell current running through the first memory cell, and a third signal to control the start of the activation of the sense amplifier;   a second word line having an interconnect structure similar to that of the first word line; and   a first monitor circuit configured to detect a first signal delay in the second word line, the first monitor circuit outputting the first signal to the sense amplifier in accordance with the first signal delay.   
     
     
         2 . The resistance change memory according to  claim 1 , wherein the second word line has an interconnect capacity similar to that of the first word line. 
     
     
         3 . The resistance change memory according to  claim 1 , further comprising a second transistor having a gate to which the second word line is connected, and having a structure similar to that of the first transistor. 
     
     
         4 . The resistance change memory according to  claim 1 , further comprising:
 a second transistor having a gate to which the second word line is connected; and   an AND circuit comprising first and second input terminals and an output terminal, one end of a current path of the second transistor being connected to the first input terminal, the first signal being input to the second input terminal.   
     
     
         5 . The resistance change memory according to  claim 4 , further comprising:
 a third word line having an interconnect structure similar to that of the first word line; and   a second monitor circuit configured to detect a second signal delay in the third word line, the second monitor circuit outputting the third signal to the sense amplifier in accordance with the second signal delay.   
     
     
         6 . The resistance change memory according to  claim 1 , further comprising a second transistor having a gate to which the second word line is connected, the first signal being supplied to the second word line,
 wherein one end of a current path of the second transistor is connected to the sense amplifier.   
     
     
         7 . The resistance change memory according to  claim 1 , further comprising a second transistor having a gate to which the second word line is connected, the first signal being supplied to the second word line,
 wherein one end of a current path of the second transistor is connected to the bit line, and the other end of the current path is connected to the sense amplifier.   
     
     
         8 . The resistance change memory according to  claim 1 , further comprising a memory cell array in which second memory cells comprising second resistance change elements and second transistors are arrayed, the first memory cell being included in the second memory cells in the memory cell array. 
     
     
         9 . The resistance change memory according to  claim 8 , wherein the second word line is disposed at the end of the memory cell array, and connected to the second transistors in the second memory cells. 
     
     
         10 . The resistance change memory according to  claim 8 , wherein the second word line is disposed in a peripheral region outside the memory cell array, and
 a third transistor which has the second word line as a gate is provided in the peripheral region.   
     
     
         11 . The resistance change memory according to  claim 1 , wherein the second word line is made of a same material as the first word line. 
     
     
         12 . The resistance change memory according to  claim 1 , wherein a constant current source is connected to the bit line during the reading operation. 
     
     
         13 . The resistance change memory according to  claim 1 , wherein the first resistance change element includes a magnetic tunnel junction (MTJ) element. 
     
     
         14 . A resistance change memory comprising:
 a first memory cell comprising a first resistance change element and a first select transistor;   a first bit line which is connected to the first memory cell and which is selected in accordance with an address signal;   a first word line which is connected to the first select transistor and which is driven in accordance with the address signal;   a second word line having an interconnect structure similar to that of the first word line;   a sense amplifier configured to read data stored in the first memory cell;   a MOS transistor connected between the first bit line and the sense amplifier;   a control circuit configured to control the reading by the sense amplifier, the control circuit outputting a first signal to control the start of precharging of the bit line, outputting, to the first and second word lines, a second signal to control a cell current running through the first memory cell, and outputting a third signal to control the start of the activation of the sense amplifier; and   a first monitor circuit configured to detect a first signal delay of the second signal in the second word line, the first monitor circuit delaying the first signal in accordance with the first signal delay and then outputting the first signal to a gate of the MOS transistor.   
     
     
         15 . The resistance change memory according to  claim 14 , wherein the second word line has an interconnect capacity similar to that of the first word line. 
     
     
         16 . The resistance change memory according to  claim 14 , further comprising a second select transistor having a gate to which the second word line is connected, and having a structure similar to that of the first select transistor. 
     
     
         17 . The resistance change memory according to  claim 14 , further comprising:
 a second select transistor having a gate to which the second word line is connected; and   an AND circuit comprising first and second input terminals and an output terminal, one end of a current path of the second select transistor being connected to the first input terminal, the first signal being input to the second input terminal.   
     
     
         18 . The resistance change memory according to  claim 14 , further comprising:
 a third word line having an interconnect structure similar to that of the first word line, the second signal being supplied to a gate of the third word line; and   a second monitor circuit configured to detect a second signal delay of the second signal in the third word line, the second monitor circuit delaying the third signal in accordance with the second signal delay and then outputting the third signal to the sense amplifier.   
     
     
         19 . The resistance change memory according to claim  14 , further comprising a memory cell array in which second memory cells comprising second resistance change elements and second select transistors are arrayed, the first memory cell being included in the second memory cells,
 wherein the second word line is disposed at the end of the memory cell array, and connected to gates of the second select transistors in the second memory cells.   
     
     
         20 . The resistance change memory according to  claim 14  comprising a magnetoresistive random access memory (MRAM).