Techniques to transmit commands to a target device

Abstract

Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.

What is claimed is: 
     
         1 . An apparatus comprising:
 logic to form at least a first bit and a second bit in a secondary data packet, wherein the first bit is to indicate whether to enter self refresh and the second bit is to indicate whether to store a frame for display into a frame buffer and wherein the secondary data packet is in compliance with a DisplayPort specification.   
     
     
         2 . The apparatus of  claim 1 , wherein the first bit is to indicate whether to enter self refresh or remain in normal operation. 
     
     
         3 . The apparatus of  claim 1 , comprising:
 logic to set the first bit to indicate to enter self refresh based at least on at least one of: a change in the system timer period, triangle or polygon rendering, any processor core is not in low power mode, any mouse activity, vertical blanking interrupts are used, or overlay is enabled.   
     
     
         4 . The apparatus of  claim 1 , wherein the second bit is to indicate whether a transmitted frame for display is identical to a previously transmitted frame for display. 
     
     
         5 . The apparatus of  claim 1 , comprising:
 logic to cause powering down of components, the components comprising one or more of: a display phase lock loop (PLL), display plane, display pipe, or display interface.   
     
     
         6 . The apparatus of  claim 1 , comprising:
 an interface communicatively coupled to the logic to form at least a first bit and a second bit in a secondary data packet;   a display controller communicatively coupled to the interface; and   a frame buffer, the display controller to cause storage of a frame for display into the frame buffer in response to an indication to enter self refresh and an indication to store a frame for display into the frame buffer.   
     
     
         7 . The apparatus of  claim 6 , comprising:
 a display communicatively coupled to the frame buffer, the display to display at least one frame for display from the frame buffer.   
     
     
         8 . The apparatus of  claim 1 , wherein the DisplayPort specification comprises DisplayPort specification version 1.1a. 
     
     
         9 . The apparatus of  claim 1 , wherein the logic comprises any or a combination of:
 one or more integrated circuits, hardwired logic, software executed by a microprocessor, or a field programmable gate array.   
     
     
         10 . At least one computer-readable medium, comprising instructions stored thereon, which, if executed by one or more processors, cause the one or more processors to:
 form at least a first bit and a second bit in a secondary data packet, wherein the first bit is to indicate whether to enter self refresh and the second bit is to indicate whether to store a frame for display into a frame buffer and wherein the secondary data packet is in compliance with a DisplayPort specification.   
     
     
         11 . The at least one computer-readable medium of  claim 10 , wherein the first bit is to indicate whether to enter self refresh or remain in normal operation. 
     
     
         12 . The at least one computer-readable medium of  claim 10 , comprising instructions stored thereon, which, if executed by one or more processors, cause the one or more processors to:
 set the first bit to indicate to enter self refresh based at least on at least one of a change in the system timer period, triangle or polygon rendering, any processor core is not in low power mode, any mouse activity, vertical blanking interrupts are used, or overlay is enabled.   
     
     
         13 . The at least one computer-readable medium of  claim 10 , wherein the second bit is to indicate whether a transmitted frame for display is identical to a previously transmitted frame for display. 
     
     
         14 . The at least one computer-readable medium of  claim 10 , comprising instructions stored thereon, which, if executed by one or more processors, cause the one or more processors to:
 cause powering down of components, the components comprising one or more of: p 1  a display phase lock loop (PLL), display plane, display pipe, or display interface.   
     
     
         15 . The at least one computer-readable medium of  claim 10 , wherein the DisplayPort specification comprises DisplayPort specification version 1.1a. 
     
     
         16 . A computer-implemented method comprising:
 forming at least a first bit and a second bit in a secondary data packet, wherein the first bit is to indicate whether to enter self refresh and the second bit is to indicate whether to store a frame for display into a frame buffer and wherein the secondary data packet is in compliance with a DisplayPort specification.   
     
     
         17 . The computer-implemented method of  claim 16 , wherein the first bit is to indicate whether to enter self refresh or remain in normal operation. 
     
     
         18 . The computer-implemented method of  claim 16 , comprising:
 setting the first bit to indicate to enter self refresh based at least on at least one of a change in the system timer period, triangle or polygon rendering, any processor core is not in low power mode, any mouse activity, vertical blanking interrupts are used, or overlay is enabled.   
     
     
         19 . The computer-implemented method of  claim 16 , wherein the second bit is to indicate whether a transmitted frame for display is identical to a previously transmitted frame for display. 
     
     
         20 . The computer-implemented method of  claim 16 , comprising:
 causing powering down of components, the components comprising one or more of: a display phase lock loop (PLL), display plane, display pipe, or display interface.   
     
     
         21 . The computer-implemented method of  claim 16 , wherein the DisplayPort specification comprises DisplayPort specification version 1.1a. 
     
     
         22 . An apparatus comprising:
 a controller to receive at least a first bit and a second bit from a secondary data packet, wherein the first bit is to indicate whether to enter self refresh and the second bit is to indicate whether to store a frame for display into a frame buffer and wherein the secondary data packet is in compliance with a DisplayPort specification.   
     
     
         23 . The apparatus of  claim 22 , comprising:
 a frame buffer, the controller to cause storage of a frame for display into the frame buffer in response to an indication to enter self refresh and an indication to store a frame for display into the frame buffer.   
     
     
         24 . The apparatus of  claim 22 , comprising:
 an interface communicatively coupled to the controller, the interface to receive the secondary data packet.   
     
     
         25 . The apparatus of  claim 23 , comprising:
 a display communicatively coupled to the frame buffer, the display to display at least one frame for display from the frame buffer.   
     
     
         26 . The apparatus of  claim 22 , wherein the first bit is to indicate whether to enter self refresh or remain in normal operation. 
     
     
         27 . The apparatus of  claim 22 , wherein the second bit is to indicate whether a transmitted frame for display is identical to a previously transmitted frame for display. 
     
     
         28 . The apparatus of  claim 22 , wherein the DisplayPort specification comprises DisplayPort specification version 1.1a. 
     
     
         29 . The apparatus of  claim 22 , wherein the controller comprises any or a combination of: one or more integrated circuits, hardwired logic, software executed by a microprocessor, or a field programmable gate array. 
     
     
         30 . At least one computer-readable medium, comprising instructions stored thereon, which, if executed by one or more processors, cause the one or more processors to:
 receive at least a first bit and a second bit from a secondary data packet, wherein the first bit is to indicate whether to enter self refresh and the second bit is to indicate whether to store a frame for display into a frame buffer and wherein the secondary data packet is in compliance with a DisplayPort specification.   
     
     
         31 . The at least one computer-readable medium of  claim 30 , wherein the first bit is to indicate whether to enter self refresh or remain in normal operation. 
     
     
         32 . The at least one computer-readable medium of  claim 30 , wherein the second bit is to indicate whether a transmitted frame for display is identical to a previously transmitted frame for display. 
     
     
         33 . The at least one computer-readable medium of  claim 30 , wherein the DisplayPort specification comprises DisplayPort specification version 1.1a. 
     
     
         34 . A computer-implemented method comprising:
 receiving at least a first bit and a second bit from a secondary data packet, wherein the first bit is to indicate whether to enter self refresh and the second bit is to indicate whether to store a frame for display into a frame buffer and wherein the secondary data packet is in compliance with a DisplayPort specification.   
     
     
         35 . The method of  claim 34 , wherein the first bit is to indicate whether to enter self refresh or remain in normal operation. 
     
     
         36 . The method of  claim 34 , wherein the second bit is to indicate whether a transmitted frame for display is identical to a previously transmitted frame for display. 
     
     
         37 . The method of  claim 34 , wherein the DisplayPort specification comprises DisplayPort specification version 1.1a.