Array substrate for liquid crystal display device and method of manufacturing the same

Abstract

An array substrate for a liquid crystal display device includes a substrate; a semiconductor layer on the substrate; a gate electrode on the semiconductor layer; source and drain electrodes on and in contact with the semiconductor layer; and an oxide layer on the gate electrode, the oxide layer including a plurality of metal atoms, wherein each of the source and drain electrodes includes a pattern of metal substantially made of the plurality of metal atoms.

What is claimed is: 
     
         1 . An array substrate for a liquid crystal display device, comprising:
 a substrate;   a semiconductor layer on the substrate;   a gate electrode on the semiconductor layer;   source and drain electrodes on and in contact with the semiconductor layer; and   an oxide layer on the gate electrode, the oxide layer including a plurality of metal atoms,   wherein each of the source and drain electrodes includes a pattern of metal substantially made of the plurality of metal atoms.   
     
     
         2 . The array substrate of  claim 1 , wherein the source electrode includes a first source pattern and a second source pattern below the first source pattern, and the drain electrode includes a first drain pattern and a second drain pattern below the first drain pattern, and
 wherein the oxide layer is located at the same layer as the second source and drain patterns.   
     
     
         3 . The array substrate of  claim 2 , wherein the first source and drain patterns has a specific resistance less than the second source and drain patterns, and has a contact resistance for a conductor greater than the second source and drain patterns. 
     
     
         4 . The array substrate of  claim 2 , wherein the first source and drain patterns are made of one of Cu, Au and Mo, and the second source and drain patterns are made of one of Al, Al alloy, Cu, Ni, Cr, Ti, Pt, Ta, Ti alloy, Mo and Mo alloy. 
     
     
         5 . The array substrate of  claim 1 , wherein the oxide layer is made of one of AlxOx, AlxOx alloy, CuxOx, NixOx, CrxOx, TixOx, PtxOx, TaxOx, TixOx alloy, MoxOx and MoxOx alloy. 
     
     
         6 . The array substrate of  claim 1 , wherein the semiconductor layer includes a channel region and source and drain regions at both sides, and wherein a first insulating layer is on the channel region. 
     
     
         7 . The array substrate of  claim 6 , wherein the gate electrode is on the first insulating layer. 
     
     
         8 . The array substrate of  claim 1 , further comprising:
 a second insulating layer that is on the source and drain electrodes and includes a contact hole exposing the drain electrode; and   a pixel electrode that is on the second insulating layer and contacts the drain electrode through the contact hole.   
     
     
         9 . A method of an array substrate for a liquid crystal display device, comprising:
 forming semiconductor layer on a substrate;   forming a gate electrode on the semiconductor layer;   forming a first metal layer and a second metal layer sequentially on the gate electrode;   patterning the first metal layer and the second metal layer to form a first metal pattern and a second metal pattern, respectively;   etching the second metal pattern to expose a portion of the first metal pattern and form a first source pattern and a first drain pattern; and   oxidizing the exposed portion of the first metal pattern to form an oxide layer, a second source pattern and a second drain pattern,   wherein the first and second source patterns form a source electrode, and the first and second drain patterns form a drain electrode.   
     
     
         10 . The method of  claim 9 , wherein forming the first and second metal patterns includes:
 forming first and second photoresist patterns on the second metal layer; and   patterning the first and second metal layers using the first and second photoresist patterns to form the first and second metal patterns.   
     
     
         11 . The method of  claim 10 , wherein the first and second photoresist patterns are formed using a halftone mask. 
     
     
         12 . The method of  claim 10 , wherein forming the second source and drain patterns includes:
 removing the first photoresist pattern and partially removing the second photoresist patterns through an ashing process, thereby forming third and fourth photoresist patterns; and   etching the second metal pattern using the third and fourth photoresist patterns to expose the portion of the first metal pattern and form the second source and drain patterns.   
     
     
         13 . The method of  claim 9 , wherein the second metal layer has a specific resistance less than the first metal layer, and has a contact resistance for a conductor greater than the first metal layer. 
     
     
         14 . The method of  claim 9 , wherein the first metal layer is made of one of Al, Al alloy, Cu, Ni, Cr, Ti, Pt, Ta, Ti alloy, Mo and Mo alloy, and the second metal layer is made of one of Cu, Au and Mo. 
     
     
         15 . The method of  claim 9 , wherein oxidizing the exposed portion of the first metal pattern to form an oxide layer is conducted using an oxygen plasma treatment or a thermal treatment under oxygen atmosphere for the exposed portion of the first metal pattern. 
     
     
         16 . The method of  claim 9 , wherein the semiconductor layer includes a channel region and source and drain regions at both sides. 
     
     
         17 . The method of  claim 16 , further comprising forming a first insulating layer on the channel region. 
     
     
         18 . The method of  claim 17 , wherein the gate electrode is on the first insulating layer. 
     
     
         19 . The method of  claim 9 , further comprising:
 forming a second insulating layer on the source and drain electrodes;   forming a contact hole in the second insulating layer, the contact hole exposing the drain electrode; and   forming a pixel electrode that is on the second insulating layer and contacts the drain electrode through the contact hole.