Pulse width modulation circuit

Abstract

In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a switching operation according to a pulse control signal and a digital signal hold circuit for fetching a digital signal. The digital signal hold circuit includes a mask signal generation circuit for generating a mask signal from the pulse control signal, the mask signal being for use in keeping the digital signal from being fetched during a time period of power-source noise occurrence caused by the switching operation, and the digital signal is not fetched during the time period of power-source noise occurrence while the digital signal is fetched during a time period of power-source noise nonoccurrence.

What is claimed is: 
     
         1 . A pulse width modulation (PWM) circuit, comprising:
 a control signal hold circuit that receives a control signal and a write enable signal; and   a PWM signal generation circuit that generates a PWM signal in accordance with the control signal hold by the control signal hold circuit,   wherein the control signal hold circuit shifts the write enable signal away from the PWM signal for a predetermined period, and   wherein the control signal hold circuit holds the control signal in accordance with the shifted write enable signal.   
     
     
         2 . The pulse width modulation circuit according to  claim 1 , wherein the control signal hold circuit shifts the write enable signal when an edge of the write enable signal is placed within the predetermined period from an edge of the PWM signal. 
     
     
         3 . The pulse width modulation circuit according to  claim 2 , wherein the control signal hold circuit shifts the edge of the write enable signal away from the edge of the PWM signal for the predetermined period. 
     
     
         4 . The pulse width modulation circuit according to  claim 1 , wherein the control signal hold circuit does not shift the write enable signal when an edge of the write enable signal is not placed within the predetermined period from an edge of the PWM signal. 
     
     
         5 . The pulse width modulation circuit according to  claim 1 , wherein the write enable signal is generated when the control signal is changed. 
     
     
         6 . The pulse width modulation circuit according to  claim 1 , wherein the control signal comprises n-bit (n is integer) signals, and the write enable signal is generated when at least one of the n-bit signals is changed. 
     
     
         7 . The pulse width modulation circuit according to  claim 1 , further comprising:
 a micro control unit (MCU),   wherein the control signal is generated by the MCU.   
     
     
         8 . The pulse width modulation circuit according to  claim 1 , further comprising:
 a digital-to-analog converter (DAC) that converts the control signal hold by the control signal hold circuit to an analog signal,   wherein the PWM signal generation circuit generates the PWM signal in accordance with the analog signal.   
     
     
         9 . The pulse width modulation circuit according to  claim 1 , wherein the predetermined period is determined by a noise generated by the PWM signal. 
     
     
         10 . The pulse width modulation circuit according to  claim 1 , wherein the predetermined period is less than a half pulse width of the PWM signal.