Dual gate fd-soi transistor

Abstract

Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

1 . A method of forming a silicon-on-insulator dual gate transistor circuit, the method comprising:
 electrically coupling together primary and secondary gates of a silicon-on-insulator dual gate transistor;   electrically coupling a source terminal of the silicon-on-insulator dual gate transistor to a first circuit element; and   electrically coupling a drain terminal of the silicon-on-insulator dual gate transistor to a second circuit element.   
     
     
         2 . The method of  claim 1  wherein the first and second circuit elements include one or more of a power supply, another electronic device, or a connection to ground. 
     
     
         3 . The method of  claim 1  wherein the dual gate transistor includes a buried oxide layer adjacent to the secondary gate. 
     
     
         4 . The method of  claim 1  wherein the dual gate transistor is an NMOS dual gate transistor, the primary and secondary gates are both coupled to a core power supply, the drain terminal is grounded, and the source terminal is coupled to a PMOS transistor. 
     
     
         5 . The method of  claim 1  wherein the dual gate transistor is an NMOS dual gate transistor, the primary and secondary gates are both coupled to an input, the drain terminal is grounded, and the source terminal is coupled to a PMOS transistor. 
     
     
         6 . The method of  claim 1  wherein the dual gate transistor is a PMOS dual gate transistor, the primary and secondary gates are both coupled to an input, the source terminal is coupled to a power supply, and the drain terminal is coupled to an NMOS transistor. 
     
     
         7 . The method of  claim 1  wherein the dual gate transistor is an NMOS dual gate transistor, the primary and secondary gates are both coupled to an input, the drain terminal is grounded, and the source terminal is coupled to an output load. 
     
     
         8 . The method of  claim 1  wherein the dual gate transistor is an NMOS dual gate transistor, the primary and secondary gates are both coupled to an input of an inverter, the drain terminal is grounded, and the source terminal is coupled to a power supply through a PMOS transistor. 
     
     
         9 . The method of  claim 1  wherein the dual gate transistor is an NMOS dual gate transistor, the primary and secondary gates are both coupled to an output of an inverter, the drain terminal is grounded, and the source terminal is coupled to a power supply through a PMOS transistor. 
     
     
         10 . The method of  claim 1  wherein the dual gate transistor is a first PMOS dual gate transistor, the primary and secondary gates are both coupled to a second PMOS dual gate transistor, the drain terminal is coupled to an NMOS dual gate transistor, and the source terminal is coupled to a power supply. 
     
     
         11 . A circuit module, comprising:
 a silicon-on-insulator dual gate transistor;   a first circuit element coupled to a source terminal of the silicon-on-insulator dual gate transistor;   a second circuit element coupled to a drain terminal of the silicon-on-insulator dual gate transistor; and   an electrical conductor extending from the primary gate to the secondary gate that electrically couples the primary and secondary gates to one another.   
     
     
         12 . The circuit module of  claim 11  wherein the dual gate transistor includes a buried oxide layer adjacent to the secondary gate. 
     
     
         13 . The circuit module of  claim 11  wherein the first circuit element is a PMOS transistor, the second circuit element is a ground connection, and the dual gate transistor is an NMOS dual gate transistor configured with the primary and secondary gates coupled to a core supply. 
     
     
         14 . The circuit module of  claim 11  wherein the first circuit element is a power supply coupled to the source through a resistor, the second circuit element is a ground connection, and the dual gate transistor is an NMOS dual gate transistor configured with primary and secondary gates coupled to an input terminal of the amplifier circuit module. 
     
     
         15 . The circuit module of  claim 11  wherein the dual gate transistor is part of a level shifter circuit in which the first circuit element is power supply coupled to the source through a PMOS transistor, the second circuit element is a ground connection, and the dual gate transistor is an NMOS dual gate transistor configured with primary and secondary gates coupled to an input terminal of an inverter. 
     
     
         16 . The circuit module of  claim 11  wherein the dual gate transistor is part of a level shifter circuit in which the first circuit element is power supply coupled to the source through a PMOS transistor, the second circuit element is a ground connection, and the dual gate transistor is an NMOS dual gate transistor configured with primary and secondary gates coupled to an output terminal of an inverter. 
     
     
         17 . An inverter circuit module, comprising:
 a PMOS dual gate transistor having primary and secondary gates coupled to an input terminal and a source terminal coupled to a power supply; and   an NMOS dual gate transistor having primary and secondary gates coupled to the input terminal, and a drain terminal coupled to ground, an output terminal of the inverter coupled to both a drain terminal of the PMOS dual gate transistor and a source terminal of the NMOS dual gate transistor.   
     
     
         18 . A pass gate comprising an NMOS dual gate transistor configured with primary and secondary gates coupled together. 
     
     
         19 . A pass gate comprising a PMOS dual gate transistor configured with primary and secondary gates coupled together. 
     
     
         20 . A method of making a silicon-on-insulator dual gate transistor, the method comprising:
 providing a silicon-on-insulator substrate including a buried oxide layer over an N-doped region;   forming a primary gate that includes a gate electrode and a gate oxide;   implanting source and drain regions with dopant ions using the primary gate as a mask;   forming a front side contact to the N-doped region for use of the N-doped region as a secondary gate; and   coupling the primary gate to the secondary gate.