US2015130064A1PendingUtilityA1

Methods of manufacturing semiconductor devices and a semiconductor structure

Assignee: IBMPriority: Feb 22, 2008Filed: Jan 21, 2015Published: May 14, 2015
Est. expiryFeb 22, 2028(~1.6 yrs left)· nominal 20-yr term from priority
H10P 14/44H10W 20/42H10W 20/033H10W 20/4403C23C 14/0641C23C 14/02H01L 23/53209H01L 23/5226
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Claims

Abstract

Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A structure comprising:
 a wafer having an edge and extreme edges; and   a trough and/or via formed within a dielectric on the wafer, wherein   the trough and/or via has a barrier of TaN (tantalum nitride) with a mol percentage of nitride (N) with respect to a total Ta plus N being from about 25% to 90%, and   the edge and extreme edges of the wafer have TaN deposited thereon with the mol percentage of N with respect to the total Ta plus N being from about 25% to 90%.   
     
     
         2 . The structure of  claim 1 , wherein the mol percentage of N with respect to the total Ta plus N is from about 30% to 35% at the edge and extreme edges of the wafer. 
     
     
         3 . The structure of  claim 1 , wherein the N leaks from a back side of the wafer to a surface of the wafer. 
     
     
         4 . The method of  claim 3 , wherein the mol percentage of the N is in a range of about 30% to 35%.

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