Processor capable of supporting multimode and multimode supporting method thereof

Abstract

Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.

What is claimed is: 
     
         1 . A processor comprising:
 front end units;   processing elements; and   a controller configured to activate a front end unit, and configured to set control information to allocate processing elements that are to process an instruction output from the activated front end unit.   
     
     
         2 . The processor of  claim 1 , wherein a number of the processing elements is greater than a number of the front end units. 
     
     
         3 . The processor of  claim 1 , wherein, before thread divergence occurs due to a conditional branch instruction, or, in response to conditional branch instructions being all terminated, the controller activates a front end unit and sets the control information to allocate all processing elements to the activated front end unit. 
     
     
         4 . The processor of  claim 1 , wherein in response to thread divergence occurring due to a conditional branch instruction, the controller activates front end units and allocates processing elements to each of the activated front end units. 
     
     
         5 . The processor of  claim 4 , wherein the controller receives from a processing element a result of processing a conditional branch instruction output from the previously activated front end unit, determines whether the thread divergence occurs, based on the received result, and in response to the determination that the thread divergence occurs, additionally activates a front end unit. 
     
     
         6 . The processor of  claim 1 , further comprising:
 an interconnector configured to, in response to the instruction being output from the activated front end unit, transmit the received instruction to a corresponding processing element, based on the control information.   
     
     
         7 . The processor of  claim 1 , wherein the control information comprises one or more of processing-element allocation information of the activated front end units, occupied program counter (PC) information, unoccupied PC information, return PC information and branch front end unit information. 
     
     
         8 . The processor of  claim 1 , wherein the controller comprises a register configured to store the control information about the activated front end unit. 
     
     
         9 . The processor of  claim 8 , wherein the register comprises as many bit-areas as a total number of processing elements to store processing-element allocation information among the control information. 
     
     
         10 . The processor of  claim 9 , wherein the controller sets bit values of bit-areas that correspond to the processing elements allocated to the activated front end unit as “1,” and sets bit values of remaining bit-areas as “0.” 
     
     
         11 . A method for supporting multi-mode processing, the method comprising:
 detecting, at a currently activated front end unit, a conditional branch instruction;   determining, at a controller, whether thread divergence occurs due to the detected conditional branch instruction;   in response to determining that the thread divergence occurs, additionally activating a front end unit; and   setting control information to allocate processing elements to the additionally activated front end unit.   
     
     
         12 . The method of  claim 11 , further comprising:
 in response to an instruction being output from an activated front end units, determining, at an interconnector, a processing element to process the output instruction, based on the control information; and   transmitting the output instruction to the determined processing element.   
     
     
         13 . The method of  claim 11 , further comprising:
 determining, at the controller, whether conditional branches processed by the additionally activated front end unit has terminated; and   in response to determining that the conditional branches have all terminated, deactivating the additionally activated front end unit.   
     
     
         14 . The method of  claim 13 , further comprising:
 setting the control information to re-allocate to the currently activated front end unit processing elements allocated to the deactivated front end unit.   
     
     
         15 . A processor comprising:
 front end units;   processing elements; and   an interconnector configured to be connected to each of the front end units and each of the processing elements, and configured to transmit an instruction of an activated front end unit among the front end units to a processing element allocated to the activated front end unit.   
     
     
         16 . The processor of  claim 15 , further comprising:
 registers corresponding to the respective front end units and configured to store control information of the respective corresponding front end units.   
     
     
         17 . The processor of  claim 16 , wherein each of the registers comprises one or more of bit areas corresponding to the respective processing elements, an area to store branch front end unit (FEU) information that indicates a relationship between the front end units, an area to store occupied program counter (PC) information that indicates a location to which an instruction jumps in response to a conditional branch being “True,” an area to store non-occupied PC information that indicates the next PC of the current PC, and an area to store return PC information that indicates a location at which an instruction returns when a conditional branch is terminated. 
     
     
         18 . The processor of  claim 17 , wherein the interconnector is configured to, in response to an instruction being output from the activated front end unit, determine a processing element to which to transmit the instruction with reference to a bit area of the register corresponding to the activated front end unit. 
     
     
         19 . A processor comprising:
 currently activated front end units, configured to execute separate conditional branches; and   a controller, configured to determine whether the conditional branches are all terminated, and in response to determining that the conditional branches are all terminated, deactivate a front end unit.   
     
     
         20 . The processor of  claim 19 , wherein the controller is further configured to re-allocate the processing elements of the deactivated front end unit to another front end unit. 
     
     
         21 . The processor of  claim 20 , wherein the controller further comprises registers associated with the respective front end units and stores control information of the respective corresponding front end units in the registers. 
     
     
         22 . The processor of  claim 21 , wherein the control information comprises processing element allocation information of the respective front end units. 
     
     
         23 . The processor of  claim 22 , wherein each of the registers further comprises as many bit-areas as a total number of processing elements to store the processing element allocation information of front end units corresponding to the registers. 
     
     
         24 . The processor of  claim 23 , wherein the setting of the control information further comprises setting bit values of a bit-area of a register associated with the additionally activated front end unit, wherein the bit values correspond to processing elements allocated to the additionally activated front end unit. 
     
     
         25 . The processor of  claim 24 , wherein the re-allocating is performed by performing a logical OR operation on the bit-areas of the deactivated front end unit and the other front end unit.