Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design

Abstract

The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.

What is claimed is: 
     
         1 . A method implemented in a programmable system for clock gating synthesis, comprising:
 identifying in an integrated circuit design having pipelined flip-flops having an expected utilization below a specified threshold;   gating the identified flip flops such that they can be shut down when not in use, said gating being performed by extraction of a stability condition for each identified flip flop in the design.   
     
     
         2 . The method as in  claim 1 , wherein the specified threshold is a utilization of a flip flop of not more than 25%. 
     
     
         3 . The method as in  claim 1 , further comprising verifying power savings achieved by such gating for each identified flip flop by performing a differential power computation of original versus gated versions of such identified flip flop in the design based upon the expected utilization of that flip flop, and incorporating the gated version into the design only when power savings are verified as being achieved. 
     
     
         4 . The method as in  claim 1 , wherein the extraction of a stability condition comprises an XOR technique in which fan-in paths for each identified flip flop are traversed until another flip flop or a primary input is reached, the stability condition of that other flip flop being generated as a delay of an XOR function of that other flip flop's input with its output, and the stability condition of primary input being generated as an XOR function of that primary input with a delay of that same primary input, the gating of the identified flip flop being a logic OR of all computed stability conditions for its fan-in paths. 
     
     
         5 . The method of  claim 1 , wherein an identified flip-flop is a first flip-flop of the pipeline with an active enable, each subsequent flip-flop in the pipeline having a stability condition computed as a logical AND of the active enable of the first flip-flop in the pipeline and a one clock cycle delay of the stability condition of the preceding flip-flop in the pipeline. 
     
     
         6 . A method implemented in a programmable system for clock gating synthesis, comprising:
 identifying in an integrated circuit design having pipelined flip-flops;   gating the identified flip flops such that they can be shut down when not in use, said gating being performed by extraction of a stability condition using an XOR technique for each identified flip flop in the design, wherein the XOR technique traverses fan-in paths for each identified flip flop until another flip flop or a primary input is reached, the stability condition of that other flip flop being generated as a delay of an XOR function of that other flip flop's input with its output, and the stability condition of primary input being generated as an XOR function of that primary input with a delay of that same primary input, the gating of the identified flip flop being a logic OR of all computed stability conditions for its fan-in paths.   
     
     
         7 . The method as in  claim 6 , wherein an identified flip-flop is a first flip-flop of the pipeline with an active enable, each subsequent flip-flop in the pipeline having a stability condition computed as a logical AND of the active enable of the first flip-flop in the pipeline and a one clock cycle delay of the stability condition of the preceding flip-flop in the pipeline. 
     
     
         8 . The method as in  claim 6 , wherein extraction of a stability condition using the XOR technique is performed only for those identified flip flops having an expected utilization below a specified threshold. 
     
     
         9 . The method as in  claim 8 , wherein the specified threshold is a utilization of a flip flop of not more than 25%. 
     
     
         10 . The method as in  claim 6 , further comprising verifying power savings achieved by such gating for each identified flip flop by performing a differential power computation of original versus gated versions of such identified flip flop in the design based upon the expected utilization of that flip flop, and incorporating the gated version into the design only when power savings are verified as being achieved.