Methods of exposing conductive vias of semiconductor devices and related semiconductor devices

Abstract

Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

What is claimed is: 
     
         1 . A method of exposing conductive vias of a semiconductor device, comprising:
 positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias;   positioning a self-planarizing isolation material on a side of the barrier material opposing the substrate, wherein an exposed surface of the self-planarizing isolation material is at least substantially planar;   removing a portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias to expose each of the conductive vias; and   stopping removal after exposing at least one laterally extending portion of the barrier material proximate the substrate.   
     
     
         2 . The method of  claim 1 , wherein positioning the barrier material over the conductive vias extending from the backside surface of the substrate to at least substantially conform to the conductive vias comprises positioning a barrier material comprising silicon nitride, silicon oxide, silicon carbide, or any combination of these over the conductive vias extending from the backside surface of the substrate to at least substantially conform to the conductive vias. 
     
     
         3 . The method of  claim 1 , wherein positioning the barrier material over the conductive vias to at least substantially conform to the conductive vias comprises depositing the barrier material to a thickness less than a protruding height of a shortest protruding portion of any of the conductive vias. 
     
     
         4 . The method of  claim 3 , wherein depositing the barrier material to the thickness less than the protruding height of the shortest protruding portion of any of the conductive vias comprises depositing the barrier material to a thickness of about 15,000 Å or less. 
     
     
         5 . The method of  claim 4 , wherein depositing the barrier material to the thickness of 15,000 Å or less comprises depositing the barrier material to a thickness of between about 800 Å and about 2,500 Å. 
     
     
         6 . The method of  claim 1 , wherein removing the portion of the self-planarizing isolation material, the portion of the barrier material, and the portion of the at least some of the conductive vias to expose each of the conductive vias comprises selectively removing a first portion of the self-planarizing isolation material at a first rate and subsequently removing a second portion of the self-planarizing isolation material, the portion of the barrier material, and the portion of the at least some of the conductive vias at a second, slower rate. 
     
     
         7 . The method of  claim 1 , further comprising stopping the removal in response to detecting a change in rate of removal of at least one of the self-planarizing isolation material, the barrier material, and the at least some of the conductive vias, a change in amount of ammonia gas present, or a change in light reflectivity of the semiconductor device. 
     
     
         8 . The method of  claim 1 , wherein stopping the removal comprises stopping the removal after exposing an entire upper surface of the barrier material extending laterally over the backside surface of the substrate. 
     
     
         9 . The method of  claim 1 , further comprising removing a portion of the substrate at the backside surface to expose portions of the conductive vias above the backside surface before conformally positioning the barrier material over the conductive vias. 
     
     
         10 . The method of  claim 1 , wherein positioning the self-planarizing isolation material on the side of the barrier material opposing the substrate comprises positioning a first self-planarizing isolation material on the side of the barrier material opposing the substrate and positioning a second, different self-planarizing isolation material on a side of the first self-planarizing isolation material opposing the barrier material. 
     
     
         11 . The method of  claim 10 , wherein positioning the first self-planarizing isolation material on the side of the barrier material opposing the substrate and positioning the second, different self-planarizing isolation material on the side of the first self-planarizing isolation material opposing the barrier material comprises positioning a first self-planarizing isolation material exhibiting a first removal rate on the side of the barrier material opposing the substrate and a second self-planarizing isolation material exhibiting a second, faster removal rate on the side of the first self-planarizing isolation material opposing the barrier material. 
     
     
         12 . The method of  claim 1 , further comprising positioning an at least substantially conformal isolation material comprising an oxide or a nitride on the side of the barrier material opposing the substrate before positioning the self-planarizing isolation material on the side of the barrier material opposing the substrate, the at least substantially conformal isolation material being interposed between the self-planarizing isolation material and the barrier material. 
     
     
         13 . A semiconductor device, comprising:
 conductive vias extending through a thickness of a substrate, each of the conductive vias comprising an exposed surface proximate a backside surface of the substrate;   a barrier material laterally adjacent to portions of the conductive vias extending from the backside surface of the substrate and extending over the backside surface of the substrate; and   a self-planarizing isolation material located on a side of at least a portion of the barrier material opposing the substrate,   wherein at least one laterally extending portion of the barrier material proximate the substrate is exposed adjacent an associated conductive via of the conductive vias.   
     
     
         14 . The semiconductor device of  claim 13 , wherein exposed surfaces of the conductive vias, the barrier material, and the self-planarizing isolation material are at least substantially coplanar. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the barrier material comprises silicon nitride, silicon oxide, silicon carbide, or any combination of these. 
     
     
         16 . The semiconductor device of  claim 13 , wherein a thickness of the barrier material is less than a difference in elevation between the backside surface of the substrate at a thickest portion of the substrate and a protruding portion of a conductive via. 
     
     
         17 . The semiconductor device of  claim 16 , wherein the thickness of the barrier material is about 15,000 Å or less. 
     
     
         18 . The semiconductor device of  claim 17 , wherein the thickness of the barrier material is between about 800 Å and about 2,500 Å. 
     
     
         19 . The semiconductor device of  claim 13 , further comprising an at least substantially conformal isolation material comprising silicon oxide interposed between the barrier material and the self-planarizing isolation material. 
     
     
         20 . The semiconductor device of  claim 13 , wherein the self-planarizing isolation material exhibits a first removal rate and the barrier material exhibits a second, slower removal rate.