Method of forming semiconductor device

Abstract

A method of forming semiconductor device uses non-implant process to form doped layers, and thus is applicable for large-size display panel. The method of forming semiconductor device uses annealing process to reduce the resistance of the doped layers, which improves the electrical property of the semiconductor device. A first dielectric layer of the semiconductor device is able to protect a semiconductor layer disposed in a first region of the substrate from being damaged during the process, and an etching stop layer of the semiconductor device is able to protect the semiconductor layer disposed in a second region of the substrate from being damaged when defining second doped layers. The first dielectric layer and the etching stop layer are formed by the same patterned dielectric layer, thus no extra process is required, fabrication cost is reduced, and yield is increased.

What is claimed is: 
     
         1 . A method of forming semiconductor device, comprising:
 providing a substrate having a first region and a second region;   forming a semiconductor layer on the substrate;   forming a doped layer on the semiconductor layer, and patterning the doped layer to form two first doped layers in the first region;   forming a patterned dielectric layer on the substrate, wherein the patterned dielectric layer comprises a first dielectric layer disposed on the semiconductor layer of the first region and the first doped layers, and an etching stop layer disposed on the semiconductor layer of the second region;   forming another doped layer on the semiconductor layer and the patterned dielectric layer;   patterning the another doped layer to form two second doped layers in the second region, and patterning the semiconductor layer to form a first semiconductor layer in the first region and a second semiconductor layer in the second region;   forming a gate insulating layer on the substrate, the gate insulating layer covering the second doped layers, the first dielectric layer and the etching stop layer;   forming a first patterned conductive layer on the gate insulating layer, wherein the first patterned conductive layer comprises a first gate electrode disposed on the gate insulating layer of the first region, and a second gate electrode disposed on the gate insulating layer of the second region; and   forming a first source electrode and a first drain electrode electrically connected to the first doped layers respectively in the first region, and a second source electrode and a second drain electrode electrically connected to the second doped layers respectively in the second region.   
     
     
         2 . The method of forming semiconductor device of  claim 1 , wherein the first doped layers and the second doped layers are formed by a non-implant process. 
     
     
         3 . The method of forming semiconductor device of  claim 2 , further comprising performing at least one annealing process on the first doped layers, the second doped layers and the semiconductor layer. 
     
     
         4 . The method of forming semiconductor device of  claim 3 , wherein the annealing process converts the semiconductor layer from an amorphous silicon layer to a polycrystalline silicon layer. 
     
     
         5 . The method of forming semiconductor device of  claim 1 , wherein the first doped layers comprise P type doped semiconductor layers, and the second doped layers comprise N type doped semiconductor layers. 
     
     
         6 . The method of forming semiconductor device of  claim 1 , further comprising:
 forming at least one inter-layered dielectric (ILD) on the gate insulating layer, the first gate electrode and the second gate electrode prior to forming the first source electrode, the first drain electrode, the second source electrode and the second drain electrode;   forming a plurality of first contact holes in the ILD, the gate insulating layer and the first dielectric layer of the first region to partially expose each of the first doped layers, respectively; and   forming a plurality of second contact holes in the ILD and the gate insulating layer of the second region to partially expose each of the second doped layers, respectively;   wherein the first source electrode and the first drain electrode are electrically connected to the first doped layers through the first contact holes respectively, and the second source electrode and the second drain electrode are electrically connected to the second doped layers through the second contact holes respectively.   
     
     
         7 . The method of forming semiconductor device of  claim 6 , further comprising forming a light-emitting device, wherein the light-emitting device comprises a first electrode, a light-emitting layer and a second electrode, and the first electrode is electrically connected to the first drain electrode. 
     
     
         8 . The method of forming semiconductor device of  claim 1 , further comprising electrically connecting the first source electrode with the second drain electrode, and electrically connecting the first gate electrode with the second gate electrode. 
     
     
         9 . The method of forming semiconductor device of  claim 1 , further comprising electrically connecting the first gate electrode with the second drain electrode.