Complementary sonos integration into cmos flow

Abstract

Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region and the first TUNM removed. A second TUNM is formed exposing a second portion of the HM in the first-SONOS region. The second portion of the HM is etched, a channel for a second SONOS device implanted through a second pad oxide overlying the first-SONOS region and the second TUNM removed. The first and second pad oxides are concurrently etched, and the HM removed.

What is claimed is: 
     
         1 . A method of manufacturing of a complementary silicon-oxide-nitride-oxide-silicon (SONOS) device, comprising:
 depositing a hardmask (HM) over a surface of a substrate including a first-SONOS region and a second-SONOS region in which a pair of complementary P-SONOS and N-SONOS are to be formed concurrently;   forming a first tunnel mask (TUNM) over the HM exposing a first portion of the HM in the second-SONOS region;   etching the first portion of the HM, implanting a first channel for a first SONOS device through a first pad oxide overlying the second-SONOS region and removing the first TUNM;   forming a second TUNM over the HM exposing a second portion of the HM in the first-SONOS region;   etching the second portion of the HM, implanting a second channel for a second SONOS device through a second pad oxide overlying the first-SONOS region and removing the second TUNM, wherein the first and second channels include doping with opposite types of dopants; and   concurrently etching the first and second pad oxides in the second-SONOS region and the first-SONOS region, and removing the HM in the first- and second-SONOS regions immediately afterwards.   
     
     
         2 . The method of  claim 1  wherein the first-SONOS region comprises a P-SONOS region and the second-SONOS region comprises an N-SONOS region. 
     
     
         3 . The method of  claim 1  wherein the first-SONOS region comprises an N-SONOS region and the second-SONOS region comprises a P-SONOS region. 
     
     
         4 . The method of  claim 1  wherein forming the second TUNM comprises depositing photoresist over the HM and wherein the first pad oxide isolates the surface of the substrate from the photoresist in the second-SONOS region. 
     
     
         5 . The method of  claim 1  wherein the first-SONOS region comprises a P-SONOS region, and further comprising implanting a Nwell in the first-SONOS region through the second pad oxide prior to removing the second TUNM. 
     
     
         6 . The method of  claim 1  wherein the second-SONOS region comprises a N-SONOS region, and further comprising implanting a Pwell in the SONOS region through the first pad oxide prior to removing the first TUNM. 
     
     
         7 . The method of  claim 1  wherein the substrate further includes a MOS region in which a number of MOS devices are to be formed. 
     
     
         8 . The method of  claim 7  wherein the number of MOS devices include a pair of complementary MOS devices. 
     
     
         9 . The method of  claim 7  further comprising prior to depositing the HM concurrently implanting a well for at least one of the number of MOS devices in the MOS region and a well for one of the pair of complementary SONOS devices in the first SONOS region or the second-SONOS region. 
     
     
         10 . The method of  claim 7  further comprising after removing the HM depositing a gate layer over ONO stacks formed in the first-SONOS region, the second SONOS region and a gate oxide (GOx) in the MOS region and patterning the gate layer to concurrently form gates for the pair of complementary SONOS devices and at least one of the number of MOS devices. 
     
     
         11 . The method of  claim 10  further comprising after removing the HM:
 forming source and drains for the pair of complementary SONOS devices and the number of MOS devices; and 
 concurrently forming a metal layer over the first-SONOS region, the second SONOS region and the MOS region to electrically couple a drain of the first SONOS device to drain of the second SONOS device, and to electrically couple a source of at least one of the pair of complementary SON OS devices to one of the number of MOS devices. 
 
     
     
         12 - 17 . (canceled) 
     
     
         18 . A method of manufacturing a SONOS device,
 comprising:   depositing a hardmask (HM) over a surface of a substrate including a MOS region in which a number of MOS devices are to be formed, a P-SONOS region and a NSONOS region in which a pair of complementary SONOS devices are to be formed;   forming a first tunnel mask (TUNM) over the HM exposing a first portion of the HM in the N-SONOS region;   etching the first portion of the HM, implanting a first channel for a N-type SONOS device through a first pad oxide overlying the N-SONOS region and removing the first TUNM;   forming a second TUNM over the HM exposing a second portion of the HM in the P-SONOS region;   etching the second portion of the HM, implanting a second channel for a P-type SONOS device through a second pad oxide overlying the P-SONOS region and removing the second TUNM, wherein the first and second channels include doping with opposite types of dopants; and   concurrently etching the first and second pad oxides in the N-SONOS region and the P-SONOS region, and concurrently removing the HM from the N-SONOS region, the P-SONOS region and the MOS region immediately afterwards.   
     
     
         19 . (canceled) 
     
     
         20 . The method of  claim 18  further comprising:
 depositing a number of dielectric layers over the surface of the substrate, the dielectric layers include a tunneling layer overlying the surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer; and 
 etching the number of dielectric layers to form dielectric stacks for the pair of complementary SONOS devices in the N-SONOS region and the P-SONOS region. 
 
     
     
         21 . The method of  claim 20  further comprising depositing a gate oxide (GOx) in the MOS region, wherein depositing the GOx comprises concurrently forming a high temperature oxide (HTO) on the blocking layer of the dielectric stacks for the pair of complementary SONOS devices. 
     
     
         22 . The method of  claim 20  further comprising depositing a gate layer over the dielectric stacks in the N-SONOS region, the P-SONOS region and the GOx in the MOS region and patterning the gate layer to concurrently form gates for the pair of complementary SONOS devices and at least one of the number of MOS devices.