Small-sized light-emitting diode chiplets and method of fabrication thereof

Abstract

Diode includes light emitting region, first metal layer, dielectric layer, and second metal layer. Light emitting diode includes n-type group III-nitride portion, p-type group III-nitride layer, and light emitting region sandwiched between n- and p-type layers. First metal layer may be coupled to p-type III-N portion and plurality of first terminals. First metal layer and p-type III-N portion may have substantially similar lateral size that is smaller than 200 micrometers. A portion of light emitting region and first metal layer may include a single via. Electrically-insulating layer may be coupled to first metal layer and sides of the single via. First terminals may be exposed from electrically-insulating layer. Second metal layer may include second terminal and may be coupled to electrically-insulating layer and to n-type III-N portion through the single via. The thickness of the diode excluding second terminal may be between 2 and 20 micrometers. Other embodiments are described.

1 . A diode chiplet comprising:
 a n-type group III-nitride portion, a p-type group III-nitride layer, and a group III-nitride light emitting region sandwiched between the n- and p-type portion;   a first metal layer coupled to the p-type III-N layer, the first metal layer and the p-type III-N layer having a substantially similar lateral size, the first metal layer being coupled to a first terminal, wherein a central portion of the light emitting region and the first metal layer includes a single via, wherein the single via is etched through the p-type III-N layer, the light emitting region, and a part of the n-type III-N layer;   an electrically-insulating layer deposited on part of the first metal layer and sides of the single via, wherein the first terminal is exposed from the electrically-insulating layer; and   a second metal layer including a second terminal, the second metal layer coupled to the n-type III-N layer through the single via, wherein a perimeter of the diode chiplet is smaller than 600 micrometers and a thickness of the diode chiplet excluding the second terminal is between 2 and 20 micrometers.   
     
     
         2 . The diode chiplet of  claim 1 , wherein the lateral size is between 10 micrometers and 50 micrometers. 
     
     
         3 . The diode chiplet of  claim 1 , wherein the n-type and p-type portion is made out of GaN and wherein the light emitting region includes at least one layer made of InGaN. 
     
     
         4 . The diode chiplet of  claim 1 , wherein, the first metal layer comprises at least one of: (i) Silver (Ag), (ii) Indium Tin Oxide (ITO) and a Distributed Bragg Reflector (DBR), (iii) Nickel Oxide (NiO) and Silver (Ag), (iv) Aluminum, (v) Nickel, (vi) Palladium (Pd), or (vii) Platinum (Pt). 
     
     
         5 . The diode chiplet of  claim 1 , wherein the second metal layer comprises at least one of: (i) Titanium (Ti) and Aluminum, (ii) Aluminum, (iii) Titanium/Gold (Ti/Au), or (iv) a layered stack of metals including: a first layer of Titanium (Ti) on the bottom of the layered stack, a second layer of Aluminum (Al), a third layer of Titanium (Ti) or Nickel (Ni), and a fourth layer of Gold (Au). 
     
     
         6 . The diode chiplet of  claim 1 , wherein the electrically-insulating material electrically isolates the second metal layer from the first metal layer, the p-type III-N layer and the light emitting region, and wherein the electrically-insulating layer includes at least one of: silicon nitride (Si x N y ), silicon oxide (Si x O y ), silicon oxynitride (Si x O y N z ), aluminum oxide (Al x O y ), tantalum oxide (Ta x O y ), or hafnium oxide (Hf x O y ). 
     
     
         7 . The diode chiplet of  claim 1 , wherein, laterally, the diode chiplet is substantially triangular in shape, is substantially stellate in shape, is substantially hexagonal in shape, is substantially quadratic in shape, or is substantially circular in shape. 
     
     
         8 . A diode chiplet comprising:
 a n-type group III-nitride portion, a p-type group III-nitride layer, and a group III-nitride light emitting region sandwiched between the n- and p-type portion;   a first metal layer having a bottom side coupled to the p-type III-N layer and a top side including a first terminal, the bottom side of the first metal layer has a lateral size that is substantially equal to the p-type III-N layer, the first terminal being centrally located above the light emitting region;   a electrically-insulating layer coupled to the top side of the first metal layer, sides of the first metal layer and sides of the p-type III-N layer, the light emitting region, and a part of the n-type III-N layer, wherein the first terminal and exposed side parts of the n-type III-N layer are exposed from the electrically-insulating layer; and   a second metal layer including a second terminal coupled to the electrically-insulating layer and to the exposed side parts of the n-type III-N portion,   wherein a perimeter of the diode chiplet is smaller than 600 micrometers and a thickness of the diode chiplet excluding the second terminal is between 2 and 20 micrometers.   
     
     
         9 . The diode chiplet of  claim 8 , wherein the lateral size is between 10 micrometers and 50 micrometers. 
     
     
         10 . The diode chiplet of  claim 8 , wherein the n-type and p-type portion is made out of GaN, and wherein the light emitting region includes at least one layer made of InGaN. 
     
     
         11 . The diode chiplet of  claim 8 , wherein the p-type III-N portion, the n-type III-N portion, and the light emitting region are equal in lateral size. 
     
     
         12 . The diode chiplet of  claim 8 , wherein the p-type III-N portion is smaller in lateral size than the n-type III-N portion. 
     
     
         13 . The diode chiplet of  claim 8 , wherein the second terminal is coupled to a portion of a bottom side of n-type III-N portion, the bottom side of the n-type III-N portion being opposite to the top side of the first metal layer. 
     
     
         14 . The diode chiplet of  claim 8 , wherein, the first metal layer comprises at least one of: (i) Silver (Ag), (ii) Indium Tin Oxide (ITO) and a Distributed Bragg Reflector (DBR), (iii) Nickel Oxide (NiO) and Silver (Ag), (iv) Aluminum, (v) Nickel, (vi) Palladium (Pd), or (vii) Platinum (Pt). 
     
     
         15 . The diode chiplet of  claim 8 , wherein the second metal layer comprises at least one of: (i) Titanium (Ti) and Aluminum, (ii) Aluminum, (iii) Titanium/Gold (Ti/Au), or (iv) a layered stack of metals including: a first layer of Titanium (Ti) on the bottom of the layered stack, a second layer of Aluminum (Al), a third layer of Titanium (Ti) or Nickel (Ni), and a fourth layer of Gold (Au) on the top of the layered stack. 
     
     
         16 . The diode chiplet of  claim 8 , wherein the electrically-insulating material electrically isolates the second metal layer from the first metal layer, the p-type III-N portion and the light emitting region, and wherein the electrically-insulating layer includes at least one of: silicon nitride (Si x N y ), silicon oxide (Si x O y ), silicon oxynitride (Si x O y N z ), aluminum oxide (Al x O y ), tantalum oxide (Ta x O y ), or hafnium oxide (Hf x O y ). 
     
     
         17 . The diode chiplet of  claim 8 , wherein, laterally, the diode chiplet is substantially triangular in shape, is substantially stellate in shape, is substantially hexagonal in shape, is substantially quadratic in shape, or is substantially circular in shape. 
     
     
         18 . A diode chiplet comprising:
 a n-type group III-nitride portion, a p-type group III-nitride layer, and a light emitting region sandwiched between the n- and p-type portion;   a first metal layer coupled to the p-type III-N layer, the first metal layer having a substantially equal lateral size to the p-type III-N layer, the first metal layer coupled to a first terminal,
 wherein a central portion of the light emitting region on a first side and the first metal layer includes a first via, wherein the first via is etched through the p-type III-N portion, the light emitting region, and a first part of the n-type III-N portion, 
 wherein a second side of the central portion of the light emitting region that is opposite to the first side includes a second via that connects to the first via, the second via is etched through a second part of the n-type III-N portion, 
 wherein the first via includes a second metal layer that is coupled to an intersection between the first and second via; 
   a electrically-insulating layer coupled to the first metal layer, the first via, and the second metal layer wherein the plurality of first terminals are exposed from the electrically-insulating layer; and   a third metal layer including a second terminal, the third metal layer coupled to the n-type III-N portion on the second side of the light emitting region and to the second metal layer through the second via,   wherein a perimeter of the diode chiplet is smaller than 600 micrometers and a thickness of the diode chiplet excluding the second terminal is between 2 and 20 micrometers.   
     
     
         19 . The diode chiplet of  claim 18 , wherein the lateral size is between 10 micrometers and 50 micrometers. 
     
     
         20 . The diode chiplet of  claim 18 , wherein the first metal layer and the plurality of first terminals are in ohmic contact with the p-type III-N portion and the second terminal is in ohmic contact with the n-type III-N portion. 
     
     
         21 . The diode chiplet of  claim 18 , wherein, the first metal layer comprises at least one of: (i) Silver (Ag), (ii) Indium Tin Oxide (ITO) and a Distributed Bragg Reflector (DBR), (iii) Nickel Oxide (NiO) and Silver (Ag), (iv) Aluminum, (v) Nickel, (vi) Palladium (Pd), or (vii) Platinum (Pt). 
     
     
         22 . The diode chiplet of  claim 18 , wherein the second metal layer comprises at least one of: (i) Titanium (Ti) and Aluminum, (ii) Aluminum, (iii) Titanium/Gold (Ti/Au), or (iv) a layered stack of metals including: a first layer of Titanium (Ti) on the bottom of the layered stack, a second layer of Aluminum (Al), a third layer of Titanium (Ti) or Nickel (Ni), and a fourth layer of Gold (Au) on the top of the layered stack. 
     
     
         23 . The diode chiplet of  claim 18 , wherein the third metal layer includes the same material as the second metal layer, and wherein the third metal layer comprises at least one of: ITO and Zinc Oxide (ZnO). 
     
     
         24 . The diode chiplet of  claim 18 , wherein the electrically-insulating layer includes at least one of: silicon nitride (Si x N y ), silicon oxide (Si x O y ), silicon oxynitride (Si x O y N z ), aluminum oxide (Al x O y ), tantalum oxide (Ta x O y ), or hafnium oxide (Hf x O y ). 
     
     
         25 . The diode chiplet of  claim 18 , wherein, laterally, the diode chiplet is substantially triangular in shape, is substantially stellate in shape, is substantially hexagonal in shape, is substantially quadratic in shape, or is substantially circular in shape.