Mixed size data processing operation

Abstract

A data processing system includes a processor core and a memory. The processor core includes processing circuitry controlled by control signals generated by decoder circuitry which decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions or arithmetic instructions) which have a first input operand of a first operand size and a second input operand of a second input operand size where the second operand size is smaller than the first operand size. The processing performed first converts the second operand so as to have the first operand size. The processing then generates a third operand using as inputs the first operand of the first operand size and the second operand now converted to have the first operand size.

1 . Apparatus for processing data comprising:
 processing circuitry configured to perform data processing operations specified by program instructions;   a plurality of registers, each of said registers storing a scalar operand; and   decoder circuitry coupled to said processing circuitry and configured to decode said program instructions to generate control signals for controlling said processing circuitry to perform data processing operations specified by said program instructions; wherein   said decoder circuitry is configured to decode a mixed operand size arithmetic instruction to generate control signals to control said processing circuitry to perform a mixed size data processing operation having:
 (i) a first input operand of a first operand size stored within a first register of said plurality of registers as specified by a first register specifying field within said mixed operand size arithmetic instruction; 
 (ii) a second input operand of a second operand size stored within a second register of said plurality of registers as specified by a second register specifying field within said mixed operand size arithmetic instruction, said second operand size being less than said first operand size; and 
 (iii) a third operand of a third operand size, 
   a parameter field within said mixed operand size arithmetic instruction indicates an operand size of the second input operand and whether the second input operand is to be zero extended or sign extended; and   said mixed size data processing operation including processing with a same effect as:
 (a) converting said second input operand from said second operand size to said first operand size in dependence on said parameter field; and 
 (b) generating said third operand in dependence upon said first input operand with said first operand size and said second input operand with said first operand size. 
   
     
     
         2 . Apparatus as claimed in  claim 1 , wherein said third operand has said first operand size. 
     
     
         3 . (canceled) 
     
     
         4 . Apparatus as claimed in  claim 1 , wherein said generating said third operand includes setting one of more result flags stored within said apparatus. 
     
     
         5 . Apparatus as claimed in  claim 4 , wherein said one or more result flags indicate one of more of:
 said third operand is a zero;   said third operand is negative;   generating said third operand included generating an unsigned carry out bit of one from said third operand; and   generating said third operand included generating a signed overflow from said third operand.   
     
     
         6 . Apparatus as claimed in  claim 1 , wherein said parameter field further indicates a shift amount of said second input operand in said converting. 
     
     
         7 . Apparatus as claimed in  claim 6 , wherein the parameter field indicates a size of the second input operand and whether the second input operand is to be zero extended or sign extended according to whether a byte, halfword, or word is specified in combination with said shift amount. 
     
     
         8 . Apparatus as claimed in  claim 6 , wherein said generating has a same effect as said shifting being performed after said second input operand has been converted to said first operand size. 
     
     
         9 . Apparatus as claimed in  claim 1 , wherein said third operand is stored within a third register as specified by a third register specifying field within said mixed operand size arithmetic instruction. 
     
     
         10 . (canceled) 
     
     
         11 . Apparatus as claimed in  claim 10 , wherein said arithmetic data operations include at least one of:
 adding said first input operand with said first operand size and said second input operand with said first input size to generate said third operand; and   subtracting said second input operand with said first operand size from said first input operand with said first operand size to generate said third operand.   
     
     
         12 . Apparatus as claimed in  claim 1 , comprising a memory having a memory address space and wherein said third operand is an address value within said memory address space, said mixed operand size arithmetic instruction performing one of a load operation and a store operation between a third register specified by register specifying field within said mixed operand size arithmetic instruction and data value stored within said memory at said address value. 
     
     
         13 . Apparatus for processing data comprising:
 processing means for performing data processing operations specified by program instructions;   a plurality of register means for storing data, each of said register means storing a scalar operand; and   decoder means coupled to said processing means for decoding said program instructions to generate control signals for controlling said processing means to perform data processing operations specified by said program instructions; wherein   said decoder means is configured to decode a mixed operand size arithmetic instruction to generate control signals to control said processing circuitry to perform a mixed size data processing operation having:
 (i) a first input operand of a first operand size stored within a first register means of said plurality of register means as specified by a first register specifying field within said mixed operand arithmetic size instruction; 
 (ii) a second input operand of a second operand size stored within a second register means of said plurality of register means as specified by a second register specifying field within said mixed operand size arithmetic instruction, said second operand size being less than said first operand size; and 
 (iii) a third operand of a third operand size, 
   a parameter field within said mixed operand size arithmetic instruction indicates an operand size of the second input operand and whether the second input operand is to be zero extended or sign extended; and   said mixed size data processing operation including processing with a same effect as:
 (a) converting said second input operand from said second operand size to said first operand size in dependence on said parameter field; and 
 (b) generating said third operand in dependence upon said first input operand with said first operand size and said second input operand with said first operand size. 
   
     
     
         14 . A method of processing data using processing circuitry configured to perform data processing operations specified by program instructions, a plurality of registers, each of said registers storing a scalar operand and decoder circuitry coupled to said processing circuitry and configured to decode said program instructions to generate control signals for controlling said processing circuitry to perform data processing operations specified by said program instructions, said method comprising the steps of:
 decoding a mixed operand size arithmetic instruction to generate control signals to control said processing circuitry to perform a mixed size data processing operation having:
 (i) a first input operand of a first operand size stored within a first register of said plurality of registers as specified by a first register specifying field within said mixed operand size arithmetic instruction; 
 (ii) a second input operand of a second operand size stored within a second register of said plurality of registers as specified by a second register specifying field within said mixed operand size arithmetic instruction, said second operand size being less than said first operand size; and 
 (iii) a third operand of a third operand size, 
   a parameter field within said mixed operand size arithmetic instruction indicates an operand size of the second input operand and whether the second input operand is to be zero extended or sign extended; and   said mixed size data processing operation including processing with a same effect as:
 (a) converting said second input operand from said second operand size to said first operand size in dependence on said parameter field; and 
 (b) generating said third operand in dependence upon said first input operand with said first operand size and said second input operand with said first operand size. 
   
     
     
         15 . A computer program product storing in non-transitory form a computer program including at least one mixed operand size arithmetic instruction for controlling a computer to perform a method as claimed in  claim 14 . 
     
     
         16 . A virtual machine comprising a computer controlled by a computer program to provide an execution environment for executing program instructions in accordance with a method as claimed in  claim 14 . 
     
     
         17 . Apparatus as claimed in  claim 13 , wherein said parameter field further indicates a shift amount of said second input operand in said converting. 
     
     
         18 . Apparatus as claimed in  claim 17 , wherein the parameter field indicates a size of the second input operand and whether the second input operand is to be zero extended or sign extended according to whether a byte, halfword, or word is specified in combination with said shift amount. 
     
     
         19 . A method of processing data as claimed in  claim 14 , wherein said parameter field further indicates a shift amount of said second input operand in said converting. 
     
     
         20 . A method of processing data as claimed in  claim 19 , wherein the parameter field indicates a size of the second input operand and whether the second input operand is to be zero extended or sign extended according to whether a byte, halfword, or word is specified in combination with said shift amount.