Less-secure processors, integrated circuits, wireless communications apparatus, methods and processes of making

Abstract

An integrated circuit ( 122 ) includes an on-chip boot ROM ( 132 ) holding boot code, a non-volatile security identification element ( 140 ) having non-volatile information determining a less secure type or more secure type, and a processor ( 130 ). The processor ( 130 ) is coupled to the on-chip boot ROM ( 132 ) and to the non-volatile security identification element ( 140 ) to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element ( 140 ). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.

1 - 14 . (canceled) 
     
     
         15 . An integrated circuit comprising:
 security monitoring circuitry; and   storage including boot code firmware including at least first and second firmware portions, each of the first and second firmware portions establishing a secure mode entry sequence and an exit from secure mode, the entry and exit bracketing configurations for respectively higher security and lower security in the corresponding first and second firmware portions, the security monitoring circuitry coupled to the storage independent of said second firmware portion to protect a space in the storage from access, the space including both the first and second firmware portions.   
     
     
         16 . The integrated circuit of  claim 15  further comprising non-volatile bits selecting one of the first and second firmware portions for execution. 
     
     
         17 . The integrated circuit of  claim 15  further comprising first non-volatile bits selecting one of the first and second firmware portions for execution, the first nonvolatile bits unprotected by said security monitoring circuitry, and further comprising second non-volatile bits from which a higher security type or lower security type is detectable, the second non-volatile bits protected from access except access in a secure mode. 
     
     
         18 . The integrated circuit of  claim 15  wherein the security monitoring circuitry is coupled to the storage to prevent execution of the second firmware portion except in the case of a hardware reset. 
     
     
         19 . The integrated circuit of  claim 15  wherein the boot code firmware further includes firmware establishing a bypass of the second firmware portion except in the case of a hardware reset. 
     
     
         20 . The integrated circuit of  claim 15  further comprising a security control register accessible by the first and second firmware portions. 
     
     
         21 . The integrated circuit of  claim 20  wherein the configuration by the first firmware portion includes different setting of the security control register from the configuration by the second firmware portion. 
     
     
         22 . The integrated circuit of  claim 15  wherein the security monitoring circuitry is responsive to a hardware reset to accept a secure mode entry sequence by the second firmware portion. 
     
     
         23 . The integrated circuit of  claim 15  wherein the security monitoring circuitry is coupled to detect execution of the secure mode entry sequence. 
     
     
         24 . The integrated circuit of  claim 15  wherein the security monitoring circuitry is responsive to a security violation to reset the integrated circuit. 
     
     
         25 . The integrated circuit of  claim 15  wherein the security monitoring circuitry responds to a security violation to produce a re-vectoring away from the protected space. 
     
     
         26 . An integrated circuit device having first and second features, comprising
 an on-chip alterable non-volatile element; and   firmware establishing at least the second feature, the second feature having a state of disablement or enablement dependent on an unaltered or altered state of the on-chip alterable non-volatile element wherein the second feature enabled includes secure mode entry followed by establishment of lower security configuration followed by secure mode exit, and the second feature disabled includes secure mode entry and establishment of higher security configuration.   
     
     
         27 . The integrated circuit of  claim 26  wherein said on-chip alterable non-volatile element has non-volatile bits that are neither manufacturer-specific nor platform-specific. 
     
     
         28 . The integrated circuit of  claim 26  further comprising a security control register for the lower security configuration, which is inaccessible after the secure mode exit.