Ballast resistor for super-high-voltage devices

Abstract

An integrated circuit including a well region, a plurality of semiconductor regions implanted in the well region, and a plurality of polysilicon regions arranged on each of the plurality of semiconductor regions. The well region has a first doping level. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. The polysilicon regions are respectively connected directly to the plurality of semiconductor regions.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a well region having a first doping level;   a plurality of semiconductor regions implanted in the well region, wherein each of the plurality of semiconductor regions has a second doping level, and wherein the second doping level is greater than the first doping level; and   a plurality of polysilicon regions arranged on each of the plurality of semiconductor regions, wherein the polysilicon regions are respectively connected directly to the plurality of semiconductor regions.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the plurality of semiconductor regions forms a drain of a metal-oxide semiconductor field-effect transistor (MOSFET). 
     
     
         3 . The integrated circuit of  claim 2 , wherein the MOSFET has a higher voltage rating and size than a signal MOSFET. 
     
     
         4 . The integrated circuit of  claim 1 , wherein the plurality of polysilicon regions have a resistance of at least one Ohm. 
     
     
         5 . The integrated circuit of  claim 1 , wherein arranging the plurality of polysilicon regions on each of the plurality of semiconductor regions degenerates conductivity and increases resistivity of the plurality of semiconductor regions. 
     
     
         6 . The integrated circuit of  claim 1 , wherein:
 the well region and the plurality of semiconductor regions have a first type of doping,   the well region is arranged on a substrate having a second type of doping, and   the second type of doping is opposite to the first type of doping.   
     
     
         7 . The integrated circuit of  claim 1 , wherein:
 the plurality of semiconductor regions is arranged along an axis,   each of the plurality of polysilicon regions has a length and a width,   the length is greater than the width, and   the length extends along the axis.   
     
     
         8 . The integrated circuit of  claim 1 , wherein:
 the plurality of semiconductor regions is arranged along an axis,   each of the plurality of polysilicon regions has a length and a width,   the width is greater than the length, and   the width is perpendicular to the axis.   
     
     
         9 . An integrated circuit, comprising:
 a well region having a first type of doping and a first doping level, wherein the well region is arranged on a substrate having a second type of doping, and wherein the second type of doping is opposite to the first type of doping;   a plurality of semiconductor regions implanted in the well region, wherein each of the plurality of semiconductor regions has the first type of doping and a second doping level, and wherein the second doping level is greater than the first doping level; and   a plurality of polysilicon regions arranged on each of the plurality of semiconductor regions, wherein the polysilicon regions are respectively connected directly to the plurality of semiconductor regions.   
     
     
         10 . The integrated circuit of  claim 9 , wherein:
 the plurality of semiconductor regions forms a drain of a metal-oxide semiconductor field-effect transistor (MOSFET), and   the MOSFET has a higher voltage rating and size than a signal MOSFET.   
     
     
         11 . The integrated circuit of  claim 9 , wherein the plurality of polysilicon regions have a resistance of at least one Ohm. 
     
     
         12 . The integrated circuit of  claim 9 , wherein arranging the plurality of polysilicon regions on each of the plurality of semiconductor regions degenerates conductivity and increases resistivity of the plurality of semiconductor regions. 
     
     
         13 . The integrated circuit of  claim 9 , wherein:
 the plurality of semiconductor regions is arranged along an axis,   each of the plurality of polysilicon regions has a length and a width,   the length is greater than the width, and   the length extends along the axis.   
     
     
         14 . The integrated circuit of  claim 9 , wherein:
 the plurality of semiconductor regions is arranged along an axis,   each of the plurality of polysilicon regions has a length and a width,   the width is greater than the length, and   the width is perpendicular to the axis.   
     
     
         15 . A metal-oxide semiconductor field-effect transistor integrated circuit comprising:
 a plurality of drain regions, wherein the plurality of drain regions includes a plurality of semiconductor regions having a first doping level, wherein the plurality of semiconductor regions is implanted in a well region having a second doping level, and wherein the first doping level is greater than the second doping level; and   a plurality of resistors respectively connected to the plurality of drain regions, wherein the plurality of resistors includes a plurality of polysilicon regions respectively arranged on each of the plurality of semiconductor regions, wherein the plurality of polysilicon regions are respectively connected directly to the plurality of semiconductor regions.   
     
     
         16 . The metal-oxide semiconductor field-effect transistor integrated circuit of  claim 15 , further comprising:
 the well region,   wherein the plurality of semiconductor regions and the well region have a first type of doping,   wherein the well region is arranged on a substrate having a second type of doping, and   wherein the second type of doping is opposite to the first type of doping.   
     
     
         17 . The metal-oxide semiconductor field-effect transistor integrated circuit of  claim 15 , wherein:
 the plurality of semiconductor regions is arranged along an axis,   each of the plurality of polysilicon regions has a length and a width,   the length is greater than the width, and   the length extends along the axis.   
     
     
         18 . The metal-oxide semiconductor field-effect transistor integrated circuit of  claim 15 , wherein:
 the plurality of semiconductor regions is arranged along an axis,   each of the plurality of polysilicon regions has a length and a width,   the width is greater than the length, and   the width is perpendicular to the axis.   
     
     
         19 . The integrated circuit of  claim 15 , wherein the plurality of polysilicon regions have a resistance of at least one Ohm. 
     
     
         20 . The integrated circuit of  claim 15 , wherein arranging the plurality of polysilicon regions on each of the plurality of semiconductor regions degenerates conductivity and increases resistivity of the plurality of semiconductor regions.