Semiconductor device including pillar transistors

Abstract

A first pillar transistor and a second pillar transistor are arranged with no other pillar transistor therebetween, a distance between a first silicon pillar in the first pillar transistor and a second silicon pillar in the second pillar transistor is smaller than a distance between a third silicon pillar in a third pillar transistor and the first silicon pillar.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first pillar transistor including a plurality of first unit pillar transistors each including a first diffusion layer on an upper portion of a first silicon pillar formed on a substrate, a second diffusion layer on a lower portion of the first silicon pillar, and a first gate electrode formed via a first gate insulator film so as to cover a surface of the first silicon pillar between the first diffusion layer and the second diffusion layer; and   a second pillar transistor including a plurality of second unit pillar transistors each including a third diffusion layer on an upper portion of a second silicon pillar formed on the substrate, a fourth diffusion layer on a lower portion of the second silicon pillar, and a second gate electrode formed via a second gate insulator film so as to cover a surface of the second silicon pillar between the third diffusion layer and the fourth diffusion layer,   wherein adjacent first unit pillar transistors from among the plurality of first unit pillar transistors are arranged so that there is a first distance between the first silicon pillars,   adjacent second unit pillar transistors are arranged to sandwich the first unit pillar transistors therebetween with a second distance between at least one second silicon pillar in the plurality of second unit pillar transistors and at least one first silicon pillar in the plurality of first unit pillar transistors, and   the first distance is smaller than the second distance.   
     
     
         2 . A semiconductor device comprising:
 a first pillar transistor including a plurality of first unit pillar transistors each including a first diffusion layer on an upper portion of a first silicon pillar formed on a substrate, a second diffusion layer on a lower portion of the first silicon pillar, and a first gate electrode formed via a first gate insulator film so as to cover a surface of the first silicon pillar between the first diffusion layer and the second diffusion layer, the first unit pillar transistors being adjacent one another; and   a second pillar transistor including a plurality of second unit pillar transistors each including a third diffusion layer on an upper portion of a second silicon pillar formed on the substrate, a fourth diffusion layer on a lower portion of the second silicon pillar, and a second gate electrode formed via a second gate insulator film so as to cover a surface of the second silicon pillar between the third diffusion layer and the fourth diffusion layer, the second unit pillar transistors being adjacent one another,   wherein adjacent first unit pillar transistors from among the plurality of first unit pillar transistors are arranged so that there is a first distance between the first silicon pillars,   adjacent second unit pillar transistors from among the plurality of second unit pillar transistors are arranged so that there is a second distance between the second silicon pillars,   at least one first silicon pillar in the plurality of first unit pillar transistors and at least one second silicon pillar in the plurality of second unit pillar transistors is arranged with a third distance therebetween, and   the first distance and the second distance are smaller than the third distance.