Semiconductor Device

Abstract

The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node. A drive transistor supplies a drive current according to the control voltage of the output node of the error amplifier from an external power supply line to an internal power supply line. When the divided voltage exceeds a predetermined voltage, a clamp circuit changes the control voltage in the direction of decreasing the drive current.

1 - 4 . (canceled) 
     
     
         5 . A semiconductor device, comprising:
 a first power supply line for a first DC voltage;   a second power supply line for a second DC voltage lower than the first DC voltage;   an N-channel Metal Oxide Semiconductor (MOS) transistor having a gate and a drain-source path coupled between the first and second power supply lines, the N-channel MOS transistor supplying a drive current from the first power supply line to the second power supply line based on a voltage of the gate;   an error amplifier, including an output node coupled to the gate of the N-channel MOS transistor, which changes the voltage of the gate of the N-channel MOS transistor toward a first voltage which increases the drive current or a second voltage which decreases the drive current based on a difference voltage between a reference voltage and the second DC voltage; and   a clamp circuit coupled between the output node of the error amplifier and the gate of the N-channel MOS transistor,   wherein, when the second DC voltage exceeds a predetermined voltage higher than the reference voltage, the clamp circuit changes the voltage of the gate of the N-channel MOS transistor toward the second voltage which decreases the drive current, and   wherein, when the second DC voltage does not exceed the predetermined voltage, the clamp circuit does not change the voltage of the gate of the N-channel MOS transistor.   
     
     
         6 . The semiconductor device according to  claim 5 ,
 wherein, when the second DC voltage exceeds the predetermined voltage, the clamp circuit decreases the voltage of the gate of the N-channel MOS transistor.   
     
     
         7 . A semiconductor device, comprising:
 a first power supply line for a first DC voltage;   a second power supply line for a second DC voltage lower than the first DC voltage;   an P-channel MOS transistor having a gate and a drain-source path coupled between the first and second power supply lines, the P-channel MOS transistor supplying a drive current from the first power supply line to the second power supply line based on a voltage of the gate;   an error amplifier, including an output node coupled to the gate of the P-channel MOS transistor, which changes the voltage of the gate of the P-channel MOS transistor toward a first voltage which increases the drive current or a second voltage which decreases the drive current based on a difference voltage between a reference voltage and the second DC voltage; and   a clamp circuit coupled between the output node of the error amplifier and the gate of the P-channel MOS transistor,   wherein, when the second DC voltage exceeds a predetermined voltage higher than the reference voltage, the clamp circuit changes the voltage of the gate of the P-channel MOS transistor toward the second voltage which decreases the drive current, and   wherein, when the second DC voltage does not exceed the predetermined voltage, the clamp circuit does not change the voltage of the gate of the P-channel MOS transistor.   
     
     
         8 . The semiconductor device according to  claim 7 ,
 wherein, when the second DC voltage exceeds the predetermined voltage, the clamp circuit increases the voltage of the gate of the P-channel MOS transistor.   
     
     
         9 . A semiconductor device, comprising:
 a first power supply line for a first DC voltage;   a second power supply line for a second DC voltage lower than the first DC voltage;   a third power supply line for a third DC voltage lower than the second DC voltage;   a Central Processing Unit (CPU) coupled between the second power supply line and the third power supply line;   an input buffer circuit coupled between the first power supply line and the third power supply line;   a MOS transistor having a gate and a drain-source path coupled between the first and second power supply lines, the MOS transistor supplying a drive current from the first power supply line to the second power supply line based on a voltage of the gate;   an error amplifier, including an output node coupled to the gate of the MOS transistor, which changes the voltage of the gate of the MOS transistor toward a first voltage which increases the drive current or a second voltage which decreases the drive current based on a difference voltage between a reference voltage and the second DC voltage; and   a clamp circuit coupled between the output node of the error amplifier and the gate of the MOS transistor,   wherein, when the second DC voltage exceeds a predetermined voltage higher than the reference voltage, the clamp circuit changes the voltage of the gate of the MOS transistor toward the second voltage which decreases the drive current, and   wherein, when the second DC voltage does not exceed the predetermined voltage, the clamp circuit does not change the voltage of the gate of the MOS transistor.   
     
     
         10 . The semiconductor device according to  claim 9 ,
 wherein the MOS transistor is an N-channel type, and   wherein, when the second DC voltage exceeds the predetermined voltage, the clamp circuit decreases the voltage of the gate of the MOS transistor.   
     
     
         11 . The semiconductor device according to  claim 9 ,
 wherein the drive transistor is a P-channel type, and   wherein, when the second DC voltage exceeds the predetermined voltage, the clamp circuit increases the voltage of the gate of the MOS transistor.