Conductive Lines and Pads and Method of Manufacturing Thereof

Abstract

A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

What is claimed is: 
     
         1 . A method for cleaning a semiconductor device, the method comprising:
 providing a dielectric layer disposed over a substrate;   providing a plurality of contaminant particles disposed at a major surface of the dielectric layer;   depositing a capping layer over the substrate, the capping layer covering the plurality of contaminant particles;   removing the capping layer and the plurality of contaminant particles in a single process step.   
     
     
         2 . The method of  claim 1 , wherein a first metal line disposed over the dielectric layer and a second metal line is disposed under the dielectric layer. 
     
     
         3 . The method of  claim 2 , wherein depositing the capping layer comprises depositing an insulating layer. 
     
     
         4 . The method of  claim 2 , wherein depositing the capping layer comprises depositing silicon nitride (SiN), a silicon oxide (SiO), a silicon carbide (SiC), or a silicon on glass (SiOG). 
     
     
         5 . The method of  claim 2 , wherein depositing the capping layer comprises depositing hafnium silicate, hafnium oxide, zirconium silicate, or zirconium oxide. 
     
     
         6 . The method of  claim 2 , wherein depositing the capping layer comprises depositing porous silicon, spin-on organic polymeric dielectrics, or spin on silicon based polymeric dielectric. 
     
     
         7 . The method of  claim 2 , wherein the first metal line comprises copper and the second metal line comprises aluminum. 
     
     
         8 . The method of  claim 1 , wherein the plurality of contaminant particles comprise metal. 
     
     
         9 . The method of  claim 1 , wherein the plurality of contaminant particles comprise an insulator. 
     
     
         10 . The method of  claim 1 , wherein the plurality of contaminant particles comprise a semiconductor. 
     
     
         11 . A method for cleaning a semiconductor device, the method comprising:
 forming an insulating layer on a substrate, the substrate having a first region and a second region;   forming a first conductive layer on the insulating layer in the first region;   forming a second conductive layer on the insulating layer in the second region;   forming a capping layer over the insulating layer, the first conductive layer and the second conductive layer so that the capping layer covers an area with a metallic contamination; and   removing the capping layer and the metallic contamination from the area.   
     
     
         12 . The method according to  claim 11 , wherein removing the capping layer comprise over-etching the capping layer by an amount of about 80% to about 120%. 
     
     
         13 . The method according to  claim 11 , wherein removing the capping layer comprise over-etching the capping layer by an amount of about 50% to about 150%. 
     
     
         14 . A method for making a semiconductor device, the method comprising:
 forming an insulating layer over a substrate, wherein the insulating layer comprises metal interconnects and wherein the insulating layer comprises a top surface;   forming a first bond pad over the top surface of the insulating layer;   forming a second bond pad over the top surface of the insulating layer; and   encasing the first bond pad with a metal.   
     
     
         15 . The method according to  claim 14 , wherein encasing the first bond pad comprises plating the first bond pad with the metal. 
     
     
         16 . The method according to  claim 15 , wherein plating the first bond pad comprises electro-less plating the first bond pad. 
     
     
         17 . The method according to  claim 14 , further comprising forming an insulating capping layer over the second bond pad and, after encasing the first bond pad with the metal, removing the insulating capping layer from the second bond pad. 
     
     
         18 . The method according to  claim 14 , wherein the first bond pad comprises copper (Cu) and the second bond pad comprises aluminum (Al). 
     
     
         19 . The method according to  claim 14 , wherein the metal includes a layer stack comprising NiMoP, NiP, CoWP, NiB, or PdCu. 
     
     
         20 . A method for making a semiconductor device, the method comprising:
 forming a first metal line over a substrate;   forming a second metal line over the substrate;   forming a capping layer directly over the first metal line and the second metal line, the capping layer being an insulating layer;   removing the capping layer over the first metal line;   forming a third metal line directly over the first metal line; and   removing the capping layer over the second metal line.   
     
     
         21 . The method according to  claim 20 , wherein the first metal line comprises copper and the second metal line does not comprise copper. 
     
     
         22 . The method according to  claim 21 , wherein the capping layer comprises silicon nitride, silicon oxide, silicon carbide or silicon on glass. 
     
     
         23 . The method according to  claim 22 , wherein the third metal line comprises NiMoP, NiP, CoWP, NiB, or PdCu. 
     
     
         24 . The method according to  claim 20 , wherein forming the third metal line comprises plating the third metal line. 
     
     
         25 . The method according to  claim 24 , wherein plating the third metal line comprises e-less plating the third metal line.