Capacitively coupled logic gate

Abstract

An electronic logic circuit uses areal capacitive coupling devices coupled together to process a set of data inputs. Each areal capacitive coupling device can be configured such that a floating gate potential of such device can be altered to at least a first state or a second state in response to receiving an input signal from the set of data inputs, which is coupled electrically to the floating gate. A majority function logic circuit (and other similar circuits) can be interconnected this way using far fewer gates than with a conventional CMOS implementation. Selective logic gates can also be enabled or disabled by configuring them effectively as memory devices.

What is claimed is: 
     
         1 . An electronic logic circuit comprising:
 a plurality of two terminal areal capacitive coupling gates coupled to process a set of data inputs;   each two terminal areal capacitive coupling gate being a single gate configured such that a voltage potential of a floating gate of such single gate can be altered in response to receiving a single input signal from said set of data inputs, said floating gate being configured to place said two terminal areal capacitive coupling gate into a first state or a second state through areal capacitive coupling to a potential associated with a first active region of such gate receiving said single input signal;   each two terminal areal capacitive coupling gate further being configured by a function select signal to be on or off so as to enable the electronic logic circuit to process and implement a majority function operation with a selected subset of two terminal areal capacitive coupling gates for a selected subset of is said set of data inputs;   an output of each of said selected subset of two terminal areal capacitive coupling gates being related to said first state or said second state, such that a plurality of separate selected outputs can be generated by said selected subset of two terminal areal capacitive gates; and   an output of each two terminal areal capacitive coupling gate of said selected subset of two terminal areal capacitive coupling gates being related to said first state or said second state, and said selected subset of interconnected two terminal areas capacitive gates being configured to generate a plurality of separate outputs from a plurality of separate ones of said set of data inputs;   wherein said plurality of separate outputs of said plurality of interconnected two terminal areal capacitive coupling gates process separate single ones of said set of data inputs and effectuate a collective output corresponding to a logic function implemented for said selected subset set of data inputs.   
     
     
         2 . The logic circuit of  claim 1 , wherein said logic function is a majority gate function implemented on a limited variable number of a maximum number of inputs to said logic circuit. 
     
     
         3 . The logic circuit of  claim 1 , wherein said two terminal areal capacitive coupling gates operate using channel hot electron injection. 
     
     
         4 . The logic circuit of  claim 1 , wherein said function select signal is hardwired by an electrical connection to an interconnect mask. 
     
     
         5 . A method of operating a logic circuit using a dual function electronic logic gate which is a single gate that employs areal capacitive coupling between a source/drain region and a floating gate comprising:
 a. enabling the single gate to perform a first circuit function within the is logic circuit when a first selection voltage is applied to an input terminal of the device coupled to said source/drain region;   b. enabling the single gate to perform a second circuit function within the logic circuit when a second selection voltage is applied to said input terminal;   wherein the first circuit function is a memory function, and second circuit function is a switching function;   wherein the dual function electronic logic gate only participates in a logic function implemented by the logic circuit when configured to perform said first circuit function; and   further wherein the first input voltage effectuating a memory function for the dual function electronic logic gate is substantially higher than said second input voltage effectuating said switching function.   
     
     
         6 . The method of  claim 5 , wherein said steps are performed for multiple dual function electronic logic gates in the logic circuit. 
     
     
         7 . The method of  claim 6 , wherein only a subset of available dual function electronic logic gates are configured with said first circuit function. 
     
     
         8 . The method of  claim 5 , wherein said first selection voltage is at least 2× said second selection voltage. 
     
     
         9 . The method of  claim 5 , wherein said first selection voltage is sufficiently high to cause hot electron injection onto the floating gate of the dual function electronic logic gate. 
     
     
         10 . The method of  claim 5 , wherein said input terminal is electrically connected by an interconnect mask to only one of said first selection voltage or second selection voltage.