Substrates With Ultra Fine Pitch Flip Chip Bumps

Abstract

A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

What is claimed is: 
     
         1 . A multilayer composite electronic structure comprising feature layers extending in an X-Y plane, each adjacent pair of feature layers being separated by an inner via layer, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, the via posts being embedded in an inner layer dielectric, the multilayer composite structure further comprising at least one outer layer of terminations comprising at least one micro bumps wherein the at least one micro bump comprises a via pillar capped with a solderable material. 
     
     
         2 . The multilayer composite electronic structure of  claim 1 , wherein the thickness of the micro bump is between 15 micron and 50 micron. 
     
     
         3 . The multilayer composite electronic structure of  claim 1 , wherein the solderable material is selected from the group consisting of lead, tin, lead-tin alloys, tin-silver alloys, tin silver copper alloys, tin copper alloys and tin copper nickel alloys. 
     
     
         4 . The multilayer composite electronic structure of  claim 1 , wherein the solderable material is tin based. 
     
     
         5 . The multilayer composite electronic structure of  claim 1 , wherein the solderable material is lead free. 
     
     
         6 . The multilayer composite electronic structure of  claim 1 , wherein the diameter of the micro bump is in a range compatible with chip bumps. 
     
     
         7 . The multilayer composite electronic structure of  claim 1 , wherein the diameter of the micro bump is in a range of 60 to 110 microns. 
     
     
         8 . The multilayer composite electronic structure of  claim 1 , wherein the diameter of the micro bump is a minimum of 25 micron. 
     
     
         9 . The multilayer composite electronic structure of  claim 1 , wherein the separation of micro bumps is a minimum of 15 micron. 
     
     
         10 . The multilayer composite electronic structure of  claim 1 , wherein the pitch of the micro bumps is 40 microns. 
     
     
         11 . The multilayer composite electronic structure of  claim 1 , wherein the outer dielectric has a smoothness of less than 100 nm. 
     
     
         12 . The multilayer composite electronic structure of  claim 1 , wherein the outer dielectric has a smoothness of less than 50 nm. 
     
     
         13 . The multilayer composite electronic structure of  claim 1 , wherein the outer dielectric is selected from the group consisting of NX04H (Sekisui), HBI-800TR67680 (Taiyo) and GX-13 (Afinomoto). 
     
     
         14 . A method of terminating a side of a multilayer composite structure having an outer layer of via posts embedded in a dielectric, comprising the steps of:
 (i) thinning away the outer layer to expose the copper vias;   (ii) sputtering a layer of copper over the thinned surface;   (iii) applying, exposing and developing a penultimate pattern of photoresist;   (iv) electroplating an external feature layer into the pattern;   (v) stripping away the penultimate pattern of photoresist;   (vi) applying, exposing and developing an ultimate pattern of photoresist corresponding to the desired pattern of micro bumps;   (vii) pattern plating copper via posts into the ultimate pattern of photoresist;   (viii) pattern plating solderable metal over the copper via posts;   (ix) stripping away the ultimate pattern of photoresist;   (x) etching away the seed layer;   (xi) laminating a dielectric outer layer;   (xiv) plasma etching the dielectric outer layer to expose the solderable cap of the via post, and   (xv) applying a finishing treatment of the solderable cap.   
     
     
         15 . The method of  claim 14  wherein the dielectric outer layer is selected from the group consisting of a film dielectric and a dry film solder mask. 
     
     
         16 . The method of  claim 14  where step (xv) comprises applying pressure to the solder cap along axis of the via post resulting in a flat coined solderable cap. 
     
     
         17 . The method of  claim 14  where step (xv) comprises applying pressure along axis of the via post together with heat to cause reflow under pressure, resulting in a flat coined solderable cap. 
     
     
         18 . The method of  claim 14  where step (xv) comprises applying heat to cause reflow without applying pressure such that the solderable cap assumes a dome shape due to surface tension. 
     
     
         19 . The method of  claim 14  where step (xiv) of plasma etching comprises exposing to ion bombardment in a low pressure atmosphere comprising ionizing at least one of the gases selected from the group consisting of oxygen, tetrafluoride carbon and fluorine. 
     
     
         20 . The method of  claim 14  further comprising step (xiii) of applying terminations on other side of the substrate. 
     
     
         21 . The method of  claim 20 , wherein applying terminations comprises:
 (a) thinning the other side to expose the ends of copper vias;   (b) sputtering a copper seed layer;   (c) applying, exposing and developing a layer of photoresist;   (d) electroplating copper pads into the photoresist;   (e) removing the photoresist, and   (f) depositing solder mask over substrate between and overlapping the copper pads.   
     
     
         22 . A method of applying solderable bumps to ends of via posts comprising electroplating the via posts into a patterned photoresist;
 plating a solderable material over the via posts, and   removing the patterned photoresist.   
     
     
         23 . The method of  claim 22  further comprising coining the solderable material. 
     
     
         24 . The method of  claim 22  further comprising reflowing the solderable material.