Drain Extended MOS Transistors With Split Channel

Abstract

A circuit including both drain-extended metal-oxide-semiconductor (DEMOS) and low-voltage metal-oxide-semiconductor (LV_MOS) devices and methods of manufacturing the same are provided. In one embodiment, DEMOS device includes a first channel, a gate, a second channel, and a drain extension, wherein the second channel is split into a first portion and a second portion, and wherein the first portion of the second channel stops under the gate and is spaced away from the drain extension. Other embodiments are also described.

What is claimed is: 
     
         1 . A drain extended metal-oxide-semiconductor (DEMOS) device comprising a first channel, a gate, a second channel, and a drain extension, wherein the second channel is split into a first portion and a second portion, and wherein the first portion of the second channel stops under the gate and is spaced away from the drain extension. 
     
     
         2 . The DEMOS device of  claim 1 , wherein doping in the second portion of the second channel is higher than doping in the first portion of the second channel. 
     
     
         3 . The DEMOS device of  claim 2 , wherein a drain junction of the device is formed between the first channel and the second portion of the second channel. 
     
     
         4 . The DEMOS device of  claim 3 , wherein the doping in the second portion of the second channel is such that a breakdown voltage of the drain junction is above 9V. 
     
     
         5 . The DEMOS device of  claim 2 , wherein the drain extension is at least partially under the gate and within the second portion of the second channel. 
     
     
         6 . The DEMOS device of  claim 1 , wherein the device is a P-type MOS (DEPMOS) device, and the first channel is in a N-type well (NWELL), and the second channel is in a deep NNWELL (DNWELL). 
     
     
         7 . The DEMOS device of  claim 1 , wherein the device is used to program or erase one or more cells in a flash memory. 
     
     
         8 . The DEMOS device of  claim 1 , wherein doping in the second channel is lower than doping in the first channel. 
     
     
         9 . The DEMOS device of  claim 1 , wherein the drain extension is formed concurrently with a MOS channel region comprising the first and second channels in a single threshold voltage (V T ) implant, and comprise dopants of the same conductivity-type and concentration. 
     
     
         10 . A drain extended metal-oxide-semiconductor (DEMOS) device comprising:
 a well of a first conductivity-type in a deep well of the first conductivity-type in a substrate of a second conductivity-type;   a channel underlying a gate stack on a substrate through which a source in the well and drain in the deep well are electrically coupled, the channel including at least a first channel in the well a second channel in the deep well; and   a drain extension through which the drain is electrically connected to the channel.   
     
     
         11 . The DEMOS device of  claim 10 , wherein the drain extension extends into the second channel of the channel underlying the gate stack. 
     
     
         12 . The DEMOS device of  claim 11 , wherein the second channel comprises a first portion between the first channel and the drain extension, and a second portion in the drain extension underlying the gate stack. 
     
     
         13 . The DEMOS device of  claim 11 , wherein the drain extension extends from the drain to the gate stack, without extending into the second channel of the channel underlying the gate stack. 
     
     
         14 . The DEMOS device of  claim 10 , wherein an interface between the well and the deep well at a surface of the substrate coincides with an edge of the gate stack, and wherein the channel underlying the gate stack comprises only the first channel in the well. 
     
     
         15 . The DEMOS device of  claim 14 , wherein the drain extension extends into the first channel of the channel underlying the gate stack. 
     
     
         16 . The DEMOS device of  claim 14 , wherein the drain extension extends from the drain to the edge of the gate stack, without extending into the first channel of the channel underlying the gate stack. 
     
     
         17 . The DEMOS device of  claim 14 , wherein the first conductivity-type is a N-type conductivity to form a N-well and deep N-well in a P-type substrate to form a DEPMOS device. 
     
     
         18 . The DEMOS device of  claim 14 , wherein the drain extension has a doping concentration lower than the drain to achieve depletion during reverse biasing of the drain junction of the device, thereby raising a breakdown voltage thereof. 
     
     
         19 . A circuit formed in a semiconductor substrate, the circuit comprising:
 at least one drain extended metal-oxide-semiconductor (DEMOS) device including:   a well of a first dopant-type in a deep well of the first dopant-type in a substrate of a second dopant-type;   a channel underlying a gate stack on the substrate through which a source in the well and drain in the deep well are electrically coupled, the channel including at least a first channel in the well; and   a drain extension between the channel and the drain through which the drain is electrically connected to the channel; and   an ESD protection circuit comprising an ESD diffusion region formed in the substrate adjacent a source or drain diffusion region of a MOS transistor in the ESD protection circuit,   wherein the drain extension and the ESD diffusion region are formed concurrently in a single ESD implant step and comprise dopants of a same conductivity-type and concentration.   
     
     
         20 . The circuit of  claim 19 , wherein the DEMOS device further comprises a second channel of the channel in the deep well underlying the gate stack.