Computer Processor Employing Operand Data With Associated Meta-Data

Abstract

A computer processor is provided that employs a plurality of operand storage elements that store operand data values and associated meta-data as unitary operand data elements as well as at least one functional unit that performs operations that produce and access the unitary operand data elements stored in the plurality of operand storage elements. The meta-data associated with a given operand data value as part of a unitary operand data element can specify type of the unitary operand data element (e.g., vector or scalar), elemental width and floating-point error flags. The meta-data can also be used to define special operand data values (e.g., Not-a-Result and None). The meta-data is useful in optimizing execution, such as in speculation and vectorized SIMD operations. The computer processor can also support a number of particular vector operations that are useful in optimizing execution of vectorized SIMD operations.

What is claimed is: 
     
         1 . A computer processor comprising:
 a plurality of operand storage elements that store operand data values and associated meta-data as unitary operand data elements; and   at least one functional unit that performs operations that access the respective unitary operand data elements stored in the plurality of operand storage elements.   
     
     
         2 . A computer processor according to  claim 1 , wherein:
 the at least one functional unit accesses the respective unitary operand data elements stored in the plurality of operand storage elements by hardware operations carried out by the computer processor that deal jointly with the operand data values and associated metadata together as unitary operand data elements.   
     
     
         3 . A computer processor according to  claim 1 , wherein:
 the meta-data associated with a given operand data value as part of a unitary operand data element specifies a type of the unitary operand data element.   
     
     
         4 . A computer processor according to  claim 3 , wherein:
 the type of the unitary operand data element is selected from the group consisting of i) a scalar operand type that represents a single scalar operand value and ii) a vector operand type that represents a number of scalar operand values.   
     
     
         5 . A computer processor according to  claim 4 , wherein:
 the single scalar operand value represented by the scalar operand type has one of a number of predefined widths in bytes.   
     
     
         6 . A computer processor according to  claim 5 , wherein:
 the meta-data associated with the given operand data value as part of the unitary operand data element of scalar operand type further specifies one of the predefined widths in bytes.   
     
     
         7 . A computer processor according to  claim 4 , wherein:
 the number of scalar operand values represented by the vector operand type each have one of a number of predefined widths in bytes.   
     
     
         8 . A computer processor according to  claim 7 , wherein:
 the meta-data associated with the given operand data value as part of the unitary operand data element of vector operand type further specifies one of the predefined widths in bytes.   
     
     
         9 . A computer processor according to  claim 1 , wherein:
 the operand data value is represented by at least one payload data element that is physically associated with the meta-data of the unitary data element.   
     
     
         10 . A computer processor according to  claim 9 , wherein:
 the meta-data is generated and physically associated with the payload data element when loading the payload data element from a memory system operably coupled to the computer processor.   
     
     
         11 . A computer processor according to  claim 9 , wherein:
 the meta-data is physically disassociated with the payload data element when storing the payload data element to a memory system operably coupled to the computer processor.   
     
     
         12 . A computer processor according to  claim 9 , wherein:
 the meta-data and at least one payload element of the unitary operand data element can be configured to represent a Not-A-Result operand that is indicative of an error condition.   
     
     
         13 . A computer processor according to  claim 12 , wherein:
 the payload element of the unitary operand data element that represents the Not-A-Result operand includes debugging information.   
     
     
         14 . A computer processor according to  claim 13 , wherein:
 the debugging information includes information that reflects the nature of the error condition and/or information that provides some indication of where in the executing program the error condition took place.   
     
     
         15 . A computer processor according to  claim 12 , wherein:
 the at least one functional unit is configured such that, when processing a speculable operation that operates on a given Not-A-Result operand, the Not-A-Result operand propagates to the result of such speculable operation.   
     
     
         16 . A computer processor according to  claim 12 , wherein:
 the at least one functional unit is configured such that, when processing a non-speculable operation that operates on a given Not-A-Result operand, the at least one functional unit generates a fault that requires special handling by the computer processor.   
     
     
         17 . A computer processor according to  claim 9 , wherein:
 the meta-data and at least one payload element of the unitary operand data element can be configured to represent a None operand that is indicative of a missing operand value.   
     
     
         18 . A computer processor according to  claim 17 , wherein:
 the payload element of the unitary operand data element that represents the None operand includes debugging information.   
     
     
         19 . A computer processor according to  claim 18 , wherein:
 the debugging information includes information that provides some indication of where in the executing program the missing operand occurred.   
     
     
         20 . A computer processor according to  claim 17 , wherein:
 the at least one functional unit is configured such that, when processing a speculable operation that operates on a given None operand, the None operand propagates to the result of such speculable operation.   
     
     
         21 . A computer processor according to  claim 17 , wherein:
 the at least one functional unit is configured such that, when processing a non-speculable operation that operates on a given None operand to update state information of the computer processor, the at least one functional unit skips the non-speculable operation and thus does not update the state information of the computer processor.   
     
     
         22 . A computer processor according to  claim 1 , wherein:
 the meta-data associated with a given operand data value as part of a unitary operand data element of a scalar operand type that represents a floating-point number specifies a set of floating-point error condition flags.   
     
     
         23 . A computer processor according to  claim 22 , wherein:
 the at least one functional unit is configured such that, when processing a floating-point operation on at least one input scalar operand that represents a floating-point number, the set of floating-point error condition flags for the at least one input scalar operand are logically combined together with the set of floating-point error condition flags that result from the floating-point operation by a Boolean OR operation in order to derive the set of floating point error condition flags for the result scalar operand.   
     
     
         24 . A computer processor according to  claim 22 , wherein:
 the at least one functional unit is configured such that, when processing a non-speculable operation on at least one scalar operand that represents a floating-point number, the set of floating-point error condition flags for the at least one scalar operand are used to update a set of global floating point error registers maintained by the computer processor.   
     
     
         25 . A computer processing system comprising:
 a computer processor according to  claim 1 ; and   a memory system configured such that the operand data value of a respective unitary operand data element stored in the plurality of operand storage elements is loaded from the memory system, and the memory system does not include meta-data associated with the operand data value of the respective unitary operand data element.   
     
     
         26 . A method for processing operand data in a computer processor, the method comprising the steps of:
 if an operation processed by the computer processor is a particular operation that specifies a control input operand that represents a Boolean value and two input operands, using hardware circuitry of the computer processor to evaluate the Boolean value of the control input operand and select one of the two input operands as a result of the particular operation based on the evaluation of the Boolean value of the control input operand.   
     
     
         27 . A method according to  claim 26 , wherein:
 the control input operand comprises a scalar Boolean value; and   the two input operands both comprise a scalar operand or a vector operand.   
     
     
         28 . A method according to  claim 26 , wherein:
 the control input operand comprises a vector of Boolean values, the two input operands both comprise a vector operand, and the hardware circuitry of the computer processor is configured to evaluate each respective Boolean value of the control input vector and select one of the two corresponding elements of the two operands as an element of a result vector of the particular operation based on the evaluation of the respective Boolean value of the control input operand vector.   
     
     
         29 . A method according to  claim 26 , wherein:
 at least one of the two input operands can represent a None operand that is indicative of a missing operand value and selectable by the particular operation; and   the computer processor is configured such that, when processing a non-speculable operation that operates on the None operand to update state information of the computer processor, the computer processor skips the non-speculable operation and thus does not update the state information of the computer processor.   
     
     
         30 . A method for processing vector operand data in a computer processor, the method comprising the steps of:
 if an operation processed by the computer processor is a particular vector operation that specifies an input vector argument of Boolean values, using hardware circuitry of the computer processor to evaluate the Boolean values of the input vector to produce a resultant vector of Boolean values with a pattern of zero or more leading false values that corresponds to the first true element in the input vector argument.   
     
     
         31 . A method according to  claim 30 , wherein:
 the input vector argument is a result of a SIMD relational operation applied to a data vector.   
     
     
         32 . A method according to  claim 30 , wherein:
 the resultant vector of Boolean values is used as a guard mask to control the execution of SIMD operations as part of a while-loop.   
     
     
         33 . A method according to  claim 32 , wherein:
 the guard mask is used such that the SIMD operations are applied only to valid elements and not to overrun elements, or are applied only to overrun elements and not to valid elements.   
     
     
         34 . A method according to  claim 30 , wherein:
 the last element of the resultant vector of Boolean values or an extra element produced by the particular operation provides an indication whether the termination condition for the while loop has been detected.   
     
     
         35 . A method for processing vector operand data in a computer processor, the method comprising the steps of:
 if an operation processed by the computer processor is a particular vector operation that specifies an input vector argument of Boolean values whose contents indicate which of a number of implied scalar iterations of a counting loop are valid and which are to be skipped, using hardware circuitry of the computer processor to employ the input vector argument as a control input vector that is processed in conjunction with two data argument vectors;   wherein one of the data arguments is a vector of data corresponding to both the correct iterations and the iterations past the end of the count loop, and the other data argument is a vector of None operands values for the iterations past the end of the counting loop; and   wherein the control input vector is processed to select one of the two corresponding elements of the two data arguments as an element of a result vector of the particular operation based on the evaluation of the respective Boolean value of the control input vector.   
     
     
         36 . A method according to  claim 35 , wherein:
 the result vector of the particular operation is used for vector iteration of the count loop and the semantics of None operand ensure that any iterations beyond the count loop have no visible program consequence.   
     
     
         37 . A method according to  claim 35 , wherein:
 the particular operation further generates a scalar Boolean value that can be tested by a conditional branch operation to close the counting loop.   
     
     
         38 . A method for processing vector operand data in a computer processor, the method comprising the steps of:
 if an operation processed by the computer processor is a particular vector operation that specifies an input vector argument of Boolean values for a number of iterations of a while loop search, wherein each Boolean value of the input vector argument indicates whether the while loop search was satisfied in the corresponding iteration, using hardware circuitry configured to produce first and second results based on the input vector argument;   wherein the first result represents a count of the leading unsatisfied iterations, and the second result represents a Boolean scalar that indicates whether any of the iterations satisfied the condition.   
     
     
         39 . A method according to  claim 38 , wherein:
 the second result can be tested by a conditional branch operation to close the while loop search.