Overload protection of a transformer loaded line driver

Abstract

A method of identifying and correcting each of the changes that may occur with wire pairs between the transmitter and receiver in Ethernet 10GBase-T cabling is provided. The method includes four wire pairs A, B, C and D, a polarity swapping and scrambler state machine that determine if the chosen pair matches the requirements for pair A. A slave Tap state machine generates a rule for correct B, C and D patterns based on a pair chosen as pair A. The cables B, C and D are iteratively swapped to rearrange the pair mapping into the polarity swap state machine, and a deskew state machine identifies the latency difference between the different pairs. If the rules are not satisfied, a new pair A is designated at the swapping state machine and the process is repeated until the rules are satisfied.

What is claimed is: 
     
         1 . A line driver circuit comprising:
 an output transistor on an integrated circuit chip, wherein the output transistor is configured to provide an output signal to a transformer coupled to a load; and   an overload detector circuit on the integrated circuit chip, wherein the overload detector circuit is configured to:
 receive the output signal; 
 compare the output signal to a threshold value range; and 
 responsive to the output signal having a value that is outside the threshold value range, providing a control signal to the transistor to reduce an amplitude of the output signal. 
   
     
     
         2 . An rate adaptation system comprising:
 a first first in, first out (FIFO) buffer configured to serially receive a first plurality data blocks via a first data bus at a rate based on a first clock, the first FIFO buffer further configured to output the first plurality of data blocks in an order received responsive to valid read requests of a plurality of read requests, at a rate based on a second clock;   a rate adaptation transmit register configured to serially provide a second plurality of data blocks from a second FIFO buffer to a second data bus at a rate based on the second clock, wherein a frequency of the first clock is greater than a frequency of the second clock; and   a barrel shift slot register configured to, responsive to the first clock, provide the first plurality of data blocks from the first FIFO buffer to the second FIFO buffer at a rate based on the second clock.